diff options
Diffstat (limited to 'deps/v8/src/x64/assembler-x64.h')
| -rw-r--r-- | deps/v8/src/x64/assembler-x64.h | 746 |
1 files changed, 347 insertions, 399 deletions
diff --git a/deps/v8/src/x64/assembler-x64.h b/deps/v8/src/x64/assembler-x64.h index 1c838b964b..a532729d15 100644 --- a/deps/v8/src/x64/assembler-x64.h +++ b/deps/v8/src/x64/assembler-x64.h @@ -81,9 +81,6 @@ namespace internal { V(r14) \ V(r15) -// The length of pushq(rbp), movp(rbp, rsp), Push(rsi) and Push(rdi). -constexpr int kNoCodeAgeSequenceLength = kPointerSize == kInt64Size ? 6 : 17; - enum RegisterCode { #define REGISTER_CODE(R) kRegCode_##R, GENERAL_REGISTERS(REGISTER_CODE) @@ -316,7 +313,7 @@ class Immediate BASE_EMBEDDED { private: int32_t value_; - RelocInfo::Mode rmode_ = RelocInfo::NONE32; + RelocInfo::Mode rmode_ = RelocInfo::NONE; friend class Assembler; }; @@ -325,7 +322,7 @@ class Immediate BASE_EMBEDDED { // ----------------------------------------------------------------------------- // Machine instruction Operands -enum ScaleFactor { +enum ScaleFactor : int8_t { times_1 = 0, times_2 = 1, times_4 = 2, @@ -334,9 +331,15 @@ enum ScaleFactor { times_pointer_size = (kPointerSize == 8) ? times_8 : times_4 }; - -class Operand BASE_EMBEDDED { +class Operand { public: + struct Data { + byte rex = 0; + byte buf[9]; + byte len = 1; // number of bytes of buf_ in use. + int8_t addend; // for rip + offset + addend. + }; + // [base + disp/r] Operand(Register base, int32_t disp); @@ -354,10 +357,12 @@ class Operand BASE_EMBEDDED { // Offset from existing memory operand. // Offset is added to existing displacement as 32-bit signed values and // this must not overflow. - Operand(const Operand& base, int32_t offset); + Operand(Operand base, int32_t offset); // [rip + disp/r] - explicit Operand(Label* label); + explicit Operand(Label* label, int addend = 0); + + Operand(const Operand&) = default; // Checks whether either base or index register is the given register. // Does not check the "reg" part of the Operand. @@ -365,33 +370,29 @@ class Operand BASE_EMBEDDED { // Queries related to the size of the generated instruction. // Whether the generated instruction will have a REX prefix. - bool requires_rex() const { return rex_ != 0; } + bool requires_rex() const { return data_.rex != 0; } // Size of the ModR/M, SIB and displacement parts of the generated // instruction. - int operand_size() const { return len_; } - - private: - byte rex_; - byte buf_[9]; - // The number of bytes of buf_ in use. - byte len_; - - // Set the ModR/M byte without an encoded 'reg' register. The - // register is encoded later as part of the emit_operand operation. - // set_modrm can be called before or after set_sib and set_disp*. - inline void set_modrm(int mod, Register rm); - - // Set the SIB byte if one is needed. Sets the length to 2 rather than 1. - inline void set_sib(ScaleFactor scale, Register index, Register base); + int operand_size() const { return data_.len; } - // Adds operand displacement fields (offsets added to the memory address). - // Needs to be called after set_sib, not before it. - inline void set_disp8(int disp); - inline void set_disp32(int disp); - inline void set_disp64(int64_t disp); // for labels. + const Data& data() const { return data_; } - friend class Assembler; + private: + const Data data_; }; +static_assert(sizeof(Operand) <= 2 * kPointerSize, + "Operand must be small enough to pass it by value"); +// Unfortunately, MSVC 2015 is broken in that both is_trivially_destructible and +// is_trivially_copy_constructible are true, but is_trivially_copyable is false. +// (status at 2018-02-26, observed on the msvc waterfall bot). +#if V8_CC_MSVC +static_assert(std::is_trivially_copy_constructible<Operand>::value && + std::is_trivially_destructible<Operand>::value, + "Operand must be trivially copyable to pass it by value"); +#else +static_assert(IS_TRIVIALLY_COPYABLE(Operand), + "Operand must be trivially copyable to pass it by value"); +#endif #define ASSEMBLER_INSTRUCTION_LIST(V) \ V(add) \ @@ -476,7 +477,7 @@ class Assembler : public AssemblerBase { // The isolate argument is unused (and may be nullptr) when skipping flushing. static inline Address target_address_at(Address pc, Address constant_pool); static inline void set_target_address_at( - Isolate* isolate, Address pc, Address constant_pool, Address target, + Address pc, Address constant_pool, Address target, ICacheFlushMode icache_flush_mode = FLUSH_ICACHE_IF_NEEDED); // Return the code target address at a call site from the return address @@ -486,23 +487,13 @@ class Assembler : public AssemblerBase { // This sets the branch destination (which is in the instruction on x64). // This is for calls and branches within generated code. inline static void deserialization_set_special_target_at( - Isolate* isolate, Address instruction_payload, Code* code, - Address target); + Address instruction_payload, Code* code, Address target); // This sets the internal reference at the pc. inline static void deserialization_set_target_internal_reference_at( - Isolate* isolate, Address pc, Address target, + Address pc, Address target, RelocInfo::Mode mode = RelocInfo::INTERNAL_REFERENCE); - static inline RelocInfo::Mode RelocInfoNone() { - if (kPointerSize == kInt64Size) { - return RelocInfo::NONE64; - } else { - DCHECK_EQ(kPointerSize, kInt32Size); - return RelocInfo::NONE32; - } - } - inline Handle<Code> code_target_object_handle_at(Address pc); inline Address runtime_entry_at(Address pc); // Number of bytes taken up by the branch target in the code. @@ -629,29 +620,29 @@ class Assembler : public AssemblerBase { // 32 bit value, the normal push will optimize the 8 bit case. void pushq_imm32(int32_t imm32); void pushq(Register src); - void pushq(const Operand& src); + void pushq(Operand src); void popq(Register dst); - void popq(const Operand& dst); + void popq(Operand dst); void enter(Immediate size); void leave(); // Moves - void movb(Register dst, const Operand& src); + void movb(Register dst, Operand src); void movb(Register dst, Immediate imm); - void movb(const Operand& dst, Register src); - void movb(const Operand& dst, Immediate imm); + void movb(Operand dst, Register src); + void movb(Operand dst, Immediate imm); // Move the low 16 bits of a 64-bit register value to a 16-bit // memory location. - void movw(Register dst, const Operand& src); - void movw(const Operand& dst, Register src); - void movw(const Operand& dst, Immediate imm); + void movw(Register dst, Operand src); + void movw(Operand dst, Register src); + void movw(Operand dst, Immediate imm); // Move the offset of the label location relative to the current // position (after the move) to the destination. - void movl(const Operand& dst, Label* src); + void movl(Operand dst, Label* src); // Loads a pointer into a register with a relocation mode. void movp(Register dst, void* ptr, RelocInfo::Mode rmode); @@ -667,20 +658,20 @@ class Assembler : public AssemblerBase { // Loads a 64-bit immediate into a register. void movq(Register dst, int64_t value, - RelocInfo::Mode rmode = RelocInfo::NONE64); + RelocInfo::Mode rmode = RelocInfo::NONE); void movq(Register dst, uint64_t value, - RelocInfo::Mode rmode = RelocInfo::NONE64); + RelocInfo::Mode rmode = RelocInfo::NONE); void movsxbl(Register dst, Register src); - void movsxbl(Register dst, const Operand& src); + void movsxbl(Register dst, Operand src); void movsxbq(Register dst, Register src); - void movsxbq(Register dst, const Operand& src); + void movsxbq(Register dst, Operand src); void movsxwl(Register dst, Register src); - void movsxwl(Register dst, const Operand& src); + void movsxwl(Register dst, Operand src); void movsxwq(Register dst, Register src); - void movsxwq(Register dst, const Operand& src); + void movsxwq(Register dst, Operand src); void movsxlq(Register dst, Register src); - void movsxlq(Register dst, const Operand& src); + void movsxlq(Register dst, Operand src); // Repeated moves. @@ -696,9 +687,9 @@ class Assembler : public AssemblerBase { // Conditional moves. void cmovq(Condition cc, Register dst, Register src); - void cmovq(Condition cc, Register dst, const Operand& src); + void cmovq(Condition cc, Register dst, Operand src); void cmovl(Condition cc, Register dst, Register src); - void cmovl(Condition cc, Register dst, const Operand& src); + void cmovl(Condition cc, Register dst, Operand src); void cmpb(Register dst, Immediate src) { immediate_arithmetic_op_8(0x7, dst, src); @@ -710,19 +701,15 @@ class Assembler : public AssemblerBase { arithmetic_op_8(0x3A, dst, src); } - void cmpb(Register dst, const Operand& src) { - arithmetic_op_8(0x3A, dst, src); - } + void cmpb(Register dst, Operand src) { arithmetic_op_8(0x3A, dst, src); } - void cmpb(const Operand& dst, Register src) { - arithmetic_op_8(0x38, src, dst); - } + void cmpb(Operand dst, Register src) { arithmetic_op_8(0x38, src, dst); } - void cmpb(const Operand& dst, Immediate src) { + void cmpb(Operand dst, Immediate src) { immediate_arithmetic_op_8(0x7, dst, src); } - void cmpw(const Operand& dst, Immediate src) { + void cmpw(Operand dst, Immediate src) { immediate_arithmetic_op_16(0x7, dst, src); } @@ -730,37 +717,33 @@ class Assembler : public AssemblerBase { immediate_arithmetic_op_16(0x7, dst, src); } - void cmpw(Register dst, const Operand& src) { - arithmetic_op_16(0x3B, dst, src); - } + void cmpw(Register dst, Operand src) { arithmetic_op_16(0x3B, dst, src); } void cmpw(Register dst, Register src) { arithmetic_op_16(0x3B, dst, src); } - void cmpw(const Operand& dst, Register src) { - arithmetic_op_16(0x39, src, dst); - } + void cmpw(Operand dst, Register src) { arithmetic_op_16(0x39, src, dst); } - void testb(Register reg, const Operand& op) { testb(op, reg); } + void testb(Register reg, Operand op) { testb(op, reg); } - void testw(Register reg, const Operand& op) { testw(op, reg); } + void testw(Register reg, Operand op) { testw(op, reg); } void andb(Register dst, Immediate src) { immediate_arithmetic_op_8(0x4, dst, src); } void decb(Register dst); - void decb(const Operand& dst); + void decb(Operand dst); // Lock prefix. void lock(); - void xchgb(Register reg, const Operand& op); - void xchgw(Register reg, const Operand& op); + void xchgb(Register reg, Operand op); + void xchgw(Register reg, Operand op); - void cmpxchgb(const Operand& dst, Register src); - void cmpxchgw(const Operand& dst, Register src); + void cmpxchgb(Operand dst, Register src); + void cmpxchgw(Operand dst, Register src); // Sign-extends rax into rdx:rax. void cqo(); @@ -769,7 +752,7 @@ class Assembler : public AssemblerBase { // Multiply eax by src, put the result in edx:eax. void mull(Register src); - void mull(const Operand& src); + void mull(Operand src); // Multiply rax by src, put the result in rdx:rax. void mulq(Register src); @@ -825,27 +808,29 @@ class Assembler : public AssemblerBase { immediate_arithmetic_op_8(0x5, dst, src); } + void sub_sp_32(uint32_t imm); + void testb(Register dst, Register src); void testb(Register reg, Immediate mask); - void testb(const Operand& op, Immediate mask); - void testb(const Operand& op, Register reg); + void testb(Operand op, Immediate mask); + void testb(Operand op, Register reg); void testw(Register dst, Register src); void testw(Register reg, Immediate mask); - void testw(const Operand& op, Immediate mask); - void testw(const Operand& op, Register reg); + void testw(Operand op, Immediate mask); + void testw(Operand op, Register reg); // Bit operations. - void bt(const Operand& dst, Register src); - void bts(const Operand& dst, Register src); + void bt(Operand dst, Register src); + void bts(Operand dst, Register src); void bsrq(Register dst, Register src); - void bsrq(Register dst, const Operand& src); + void bsrq(Register dst, Operand src); void bsrl(Register dst, Register src); - void bsrl(Register dst, const Operand& src); + void bsrl(Register dst, Operand src); void bsfq(Register dst, Register src); - void bsfq(Register dst, const Operand& src); + void bsfq(Register dst, Operand src); void bsfl(Register dst, Register src); - void bsfl(Register dst, const Operand& src); + void bsfl(Register dst, Operand src); // Miscellaneous void clc(); @@ -859,7 +844,7 @@ class Assembler : public AssemblerBase { void setcc(Condition cc, Register reg); void pshufw(XMMRegister dst, XMMRegister src, uint8_t shuffle); - void pshufw(XMMRegister dst, const Operand& src, uint8_t shuffle); + void pshufw(XMMRegister dst, Operand src, uint8_t shuffle); // Label operations & relative jumps (PPUM Appendix D) // @@ -906,7 +891,7 @@ class Assembler : public AssemblerBase { // Jump near absolute indirect (r64) void jmp(Register adr); - void jmp(const Operand& src); + void jmp(Operand src); // Conditional jumps void j(Condition cc, @@ -923,23 +908,23 @@ class Assembler : public AssemblerBase { void fldpi(); void fldln2(); - void fld_s(const Operand& adr); - void fld_d(const Operand& adr); + void fld_s(Operand adr); + void fld_d(Operand adr); - void fstp_s(const Operand& adr); - void fstp_d(const Operand& adr); + void fstp_s(Operand adr); + void fstp_d(Operand adr); void fstp(int index); - void fild_s(const Operand& adr); - void fild_d(const Operand& adr); + void fild_s(Operand adr); + void fild_d(Operand adr); - void fist_s(const Operand& adr); + void fist_s(Operand adr); - void fistp_s(const Operand& adr); - void fistp_d(const Operand& adr); + void fistp_s(Operand adr); + void fistp_d(Operand adr); - void fisttp_s(const Operand& adr); - void fisttp_d(const Operand& adr); + void fisttp_s(Operand adr); + void fisttp_d(Operand adr); void fabs(); void fchs(); @@ -949,7 +934,7 @@ class Assembler : public AssemblerBase { void fmul(int i); void fdiv(int i); - void fisub_s(const Operand& adr); + void fisub_s(Operand adr); void faddp(int i = 1); void fsubp(int i = 1); @@ -988,24 +973,24 @@ class Assembler : public AssemblerBase { // SSE instructions void addss(XMMRegister dst, XMMRegister src); - void addss(XMMRegister dst, const Operand& src); + void addss(XMMRegister dst, Operand src); void subss(XMMRegister dst, XMMRegister src); - void subss(XMMRegister dst, const Operand& src); + void subss(XMMRegister dst, Operand src); void mulss(XMMRegister dst, XMMRegister src); - void mulss(XMMRegister dst, const Operand& src); + void mulss(XMMRegister dst, Operand src); void divss(XMMRegister dst, XMMRegister src); - void divss(XMMRegister dst, const Operand& src); + void divss(XMMRegister dst, Operand src); void maxss(XMMRegister dst, XMMRegister src); - void maxss(XMMRegister dst, const Operand& src); + void maxss(XMMRegister dst, Operand src); void minss(XMMRegister dst, XMMRegister src); - void minss(XMMRegister dst, const Operand& src); + void minss(XMMRegister dst, Operand src); void sqrtss(XMMRegister dst, XMMRegister src); - void sqrtss(XMMRegister dst, const Operand& src); + void sqrtss(XMMRegister dst, Operand src); void ucomiss(XMMRegister dst, XMMRegister src); - void ucomiss(XMMRegister dst, const Operand& src); + void ucomiss(XMMRegister dst, Operand src); void movaps(XMMRegister dst, XMMRegister src); // Don't use this unless it's important to keep the @@ -1014,48 +999,48 @@ class Assembler : public AssemblerBase { // values in xmm registers. void movss(XMMRegister dst, XMMRegister src); - void movss(XMMRegister dst, const Operand& src); - void movss(const Operand& dst, XMMRegister src); + void movss(XMMRegister dst, Operand src); + void movss(Operand dst, XMMRegister src); void shufps(XMMRegister dst, XMMRegister src, byte imm8); - void cvttss2si(Register dst, const Operand& src); + void cvttss2si(Register dst, Operand src); void cvttss2si(Register dst, XMMRegister src); - void cvtlsi2ss(XMMRegister dst, const Operand& src); + void cvtlsi2ss(XMMRegister dst, Operand src); void cvtlsi2ss(XMMRegister dst, Register src); void andps(XMMRegister dst, XMMRegister src); - void andps(XMMRegister dst, const Operand& src); + void andps(XMMRegister dst, Operand src); void orps(XMMRegister dst, XMMRegister src); - void orps(XMMRegister dst, const Operand& src); + void orps(XMMRegister dst, Operand src); void xorps(XMMRegister dst, XMMRegister src); - void xorps(XMMRegister dst, const Operand& src); + void xorps(XMMRegister dst, Operand src); void addps(XMMRegister dst, XMMRegister src); - void addps(XMMRegister dst, const Operand& src); + void addps(XMMRegister dst, Operand src); void subps(XMMRegister dst, XMMRegister src); - void subps(XMMRegister dst, const Operand& src); + void subps(XMMRegister dst, Operand src); void mulps(XMMRegister dst, XMMRegister src); - void mulps(XMMRegister dst, const Operand& src); + void mulps(XMMRegister dst, Operand src); void divps(XMMRegister dst, XMMRegister src); - void divps(XMMRegister dst, const Operand& src); + void divps(XMMRegister dst, Operand src); void movmskps(Register dst, XMMRegister src); void vinstr(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2, SIMDPrefix pp, LeadingOpcode m, VexW w); - void vinstr(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2, + void vinstr(byte op, XMMRegister dst, XMMRegister src1, Operand src2, SIMDPrefix pp, LeadingOpcode m, VexW w); // SSE2 instructions void sse2_instr(XMMRegister dst, XMMRegister src, byte prefix, byte escape, byte opcode); - void sse2_instr(XMMRegister dst, const Operand& src, byte prefix, byte escape, + void sse2_instr(XMMRegister dst, Operand src, byte prefix, byte escape, byte opcode); #define DECLARE_SSE2_INSTRUCTION(instruction, prefix, escape, opcode) \ void instruction(XMMRegister dst, XMMRegister src) { \ sse2_instr(dst, src, 0x##prefix, 0x##escape, 0x##opcode); \ } \ - void instruction(XMMRegister dst, const Operand& src) { \ + void instruction(XMMRegister dst, Operand src) { \ sse2_instr(dst, src, 0x##prefix, 0x##escape, 0x##opcode); \ } @@ -1066,8 +1051,7 @@ class Assembler : public AssemblerBase { void v##instruction(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \ vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape, kW0); \ } \ - void v##instruction(XMMRegister dst, XMMRegister src1, \ - const Operand& src2) { \ + void v##instruction(XMMRegister dst, XMMRegister src1, Operand src2) { \ vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape, kW0); \ } @@ -1075,20 +1059,20 @@ class Assembler : public AssemblerBase { #undef DECLARE_SSE2_AVX_INSTRUCTION // SSE3 - void lddqu(XMMRegister dst, const Operand& src); + void lddqu(XMMRegister dst, Operand src); // SSSE3 void ssse3_instr(XMMRegister dst, XMMRegister src, byte prefix, byte escape1, byte escape2, byte opcode); - void ssse3_instr(XMMRegister dst, const Operand& src, byte prefix, - byte escape1, byte escape2, byte opcode); + void ssse3_instr(XMMRegister dst, Operand src, byte prefix, byte escape1, + byte escape2, byte opcode); #define DECLARE_SSSE3_INSTRUCTION(instruction, prefix, escape1, escape2, \ opcode) \ void instruction(XMMRegister dst, XMMRegister src) { \ ssse3_instr(dst, src, 0x##prefix, 0x##escape1, 0x##escape2, 0x##opcode); \ } \ - void instruction(XMMRegister dst, const Operand& src) { \ + void instruction(XMMRegister dst, Operand src) { \ ssse3_instr(dst, src, 0x##prefix, 0x##escape1, 0x##escape2, 0x##opcode); \ } @@ -1098,14 +1082,14 @@ class Assembler : public AssemblerBase { // SSE4 void sse4_instr(XMMRegister dst, XMMRegister src, byte prefix, byte escape1, byte escape2, byte opcode); - void sse4_instr(XMMRegister dst, const Operand& src, byte prefix, - byte escape1, byte escape2, byte opcode); + void sse4_instr(XMMRegister dst, Operand src, byte prefix, byte escape1, + byte escape2, byte opcode); #define DECLARE_SSE4_INSTRUCTION(instruction, prefix, escape1, escape2, \ opcode) \ void instruction(XMMRegister dst, XMMRegister src) { \ sse4_instr(dst, src, 0x##prefix, 0x##escape1, 0x##escape2, 0x##opcode); \ } \ - void instruction(XMMRegister dst, const Operand& src) { \ + void instruction(XMMRegister dst, Operand src) { \ sse4_instr(dst, src, 0x##prefix, 0x##escape1, 0x##escape2, 0x##opcode); \ } @@ -1117,8 +1101,7 @@ class Assembler : public AssemblerBase { void v##instruction(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \ vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape1##escape2, kW0); \ } \ - void v##instruction(XMMRegister dst, XMMRegister src1, \ - const Operand& src2) { \ + void v##instruction(XMMRegister dst, XMMRegister src1, Operand src2) { \ vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape1##escape2, kW0); \ } @@ -1127,7 +1110,7 @@ class Assembler : public AssemblerBase { #undef DECLARE_SSE34_AVX_INSTRUCTION void movd(XMMRegister dst, Register src); - void movd(XMMRegister dst, const Operand& src); + void movd(XMMRegister dst, Operand src); void movd(Register dst, XMMRegister src); void movq(XMMRegister dst, Register src); void movq(Register dst, XMMRegister src); @@ -1139,18 +1122,18 @@ class Assembler : public AssemblerBase { // values in xmm registers. void movsd(XMMRegister dst, XMMRegister src); - void movsd(const Operand& dst, XMMRegister src); - void movsd(XMMRegister dst, const Operand& src); + void movsd(Operand dst, XMMRegister src); + void movsd(XMMRegister dst, Operand src); - void movdqa(const Operand& dst, XMMRegister src); - void movdqa(XMMRegister dst, const Operand& src); + void movdqa(Operand dst, XMMRegister src); + void movdqa(XMMRegister dst, Operand src); - void movdqu(const Operand& dst, XMMRegister src); - void movdqu(XMMRegister dst, const Operand& src); + void movdqu(Operand dst, XMMRegister src); + void movdqu(XMMRegister dst, Operand src); void movapd(XMMRegister dst, XMMRegister src); - void movupd(XMMRegister dst, const Operand& src); - void movupd(const Operand& dst, XMMRegister src); + void movupd(XMMRegister dst, Operand src); + void movupd(Operand dst, XMMRegister src); void psllq(XMMRegister reg, byte imm8); void psrlq(XMMRegister reg, byte imm8); @@ -1161,98 +1144,96 @@ class Assembler : public AssemblerBase { void psraw(XMMRegister reg, byte imm8); void psrad(XMMRegister reg, byte imm8); - void cvttsd2si(Register dst, const Operand& src); + void cvttsd2si(Register dst, Operand src); void cvttsd2si(Register dst, XMMRegister src); void cvttss2siq(Register dst, XMMRegister src); - void cvttss2siq(Register dst, const Operand& src); + void cvttss2siq(Register dst, Operand src); void cvttsd2siq(Register dst, XMMRegister src); - void cvttsd2siq(Register dst, const Operand& src); + void cvttsd2siq(Register dst, Operand src); - void cvtlsi2sd(XMMRegister dst, const Operand& src); + void cvtlsi2sd(XMMRegister dst, Operand src); void cvtlsi2sd(XMMRegister dst, Register src); - void cvtqsi2ss(XMMRegister dst, const Operand& src); + void cvtqsi2ss(XMMRegister dst, Operand src); void cvtqsi2ss(XMMRegister dst, Register src); - void cvtqsi2sd(XMMRegister dst, const Operand& src); + void cvtqsi2sd(XMMRegister dst, Operand src); void cvtqsi2sd(XMMRegister dst, Register src); void cvtss2sd(XMMRegister dst, XMMRegister src); - void cvtss2sd(XMMRegister dst, const Operand& src); + void cvtss2sd(XMMRegister dst, Operand src); void cvtsd2ss(XMMRegister dst, XMMRegister src); - void cvtsd2ss(XMMRegister dst, const Operand& src); + void cvtsd2ss(XMMRegister dst, Operand src); void cvtsd2si(Register dst, XMMRegister src); void cvtsd2siq(Register dst, XMMRegister src); void addsd(XMMRegister dst, XMMRegister src); - void addsd(XMMRegister dst, const Operand& src); + void addsd(XMMRegister dst, Operand src); void subsd(XMMRegister dst, XMMRegister src); - void subsd(XMMRegister dst, const Operand& src); + void subsd(XMMRegister dst, Operand src); void mulsd(XMMRegister dst, XMMRegister src); - void mulsd(XMMRegister dst, const Operand& src); + void mulsd(XMMRegister dst, Operand src); void divsd(XMMRegister dst, XMMRegister src); - void divsd(XMMRegister dst, const Operand& src); + void divsd(XMMRegister dst, Operand src); void maxsd(XMMRegister dst, XMMRegister src); - void maxsd(XMMRegister dst, const Operand& src); + void maxsd(XMMRegister dst, Operand src); void minsd(XMMRegister dst, XMMRegister src); - void minsd(XMMRegister dst, const Operand& src); + void minsd(XMMRegister dst, Operand src); void andpd(XMMRegister dst, XMMRegister src); - void andpd(XMMRegister dst, const Operand& src); + void andpd(XMMRegister dst, Operand src); void orpd(XMMRegister dst, XMMRegister src); - void orpd(XMMRegister dst, const Operand& src); + void orpd(XMMRegister dst, Operand src); void xorpd(XMMRegister dst, XMMRegister src); - void xorpd(XMMRegister dst, const Operand& src); + void xorpd(XMMRegister dst, Operand src); void sqrtsd(XMMRegister dst, XMMRegister src); - void sqrtsd(XMMRegister dst, const Operand& src); + void sqrtsd(XMMRegister dst, Operand src); void haddps(XMMRegister dst, XMMRegister src); - void haddps(XMMRegister dst, const Operand& src); + void haddps(XMMRegister dst, Operand src); void ucomisd(XMMRegister dst, XMMRegister src); - void ucomisd(XMMRegister dst, const Operand& src); + void ucomisd(XMMRegister dst, Operand src); void cmpltsd(XMMRegister dst, XMMRegister src); void movmskpd(Register dst, XMMRegister src); void punpckldq(XMMRegister dst, XMMRegister src); - void punpckldq(XMMRegister dst, const Operand& src); + void punpckldq(XMMRegister dst, Operand src); void punpckhdq(XMMRegister dst, XMMRegister src); // SSE 4.1 instruction void insertps(XMMRegister dst, XMMRegister src, byte imm8); void extractps(Register dst, XMMRegister src, byte imm8); void pextrb(Register dst, XMMRegister src, int8_t imm8); - void pextrb(const Operand& dst, XMMRegister src, int8_t imm8); + void pextrb(Operand dst, XMMRegister src, int8_t imm8); void pextrw(Register dst, XMMRegister src, int8_t imm8); - void pextrw(const Operand& dst, XMMRegister src, int8_t imm8); + void pextrw(Operand dst, XMMRegister src, int8_t imm8); void pextrd(Register dst, XMMRegister src, int8_t imm8); - void pextrd(const Operand& dst, XMMRegister src, int8_t imm8); + void pextrd(Operand dst, XMMRegister src, int8_t imm8); void pinsrb(XMMRegister dst, Register src, int8_t imm8); - void pinsrb(XMMRegister dst, const Operand& src, int8_t imm8); + void pinsrb(XMMRegister dst, Operand src, int8_t imm8); void pinsrw(XMMRegister dst, Register src, int8_t imm8); - void pinsrw(XMMRegister dst, const Operand& src, int8_t imm8); + void pinsrw(XMMRegister dst, Operand src, int8_t imm8); void pinsrd(XMMRegister dst, Register src, int8_t imm8); - void pinsrd(XMMRegister dst, const Operand& src, int8_t imm8); + void pinsrd(XMMRegister dst, Operand src, int8_t imm8); void roundss(XMMRegister dst, XMMRegister src, RoundingMode mode); void roundsd(XMMRegister dst, XMMRegister src, RoundingMode mode); void cmpps(XMMRegister dst, XMMRegister src, int8_t cmp); - void cmpps(XMMRegister dst, const Operand& src, int8_t cmp); + void cmpps(XMMRegister dst, Operand src, int8_t cmp); void cmppd(XMMRegister dst, XMMRegister src, int8_t cmp); - void cmppd(XMMRegister dst, const Operand& src, int8_t cmp); + void cmppd(XMMRegister dst, Operand src, int8_t cmp); #define SSE_CMP_P(instr, imm8) \ void instr##ps(XMMRegister dst, XMMRegister src) { cmpps(dst, src, imm8); } \ - void instr##ps(XMMRegister dst, const Operand& src) { \ - cmpps(dst, src, imm8); \ - } \ + void instr##ps(XMMRegister dst, Operand src) { cmpps(dst, src, imm8); } \ void instr##pd(XMMRegister dst, XMMRegister src) { cmppd(dst, src, imm8); } \ - void instr##pd(XMMRegister dst, const Operand& src) { cmppd(dst, src, imm8); } + void instr##pd(XMMRegister dst, Operand src) { cmppd(dst, src, imm8); } SSE_CMP_P(cmpeq, 0x0); SSE_CMP_P(cmplt, 0x1); @@ -1264,25 +1245,25 @@ class Assembler : public AssemblerBase { #undef SSE_CMP_P void minps(XMMRegister dst, XMMRegister src); - void minps(XMMRegister dst, const Operand& src); + void minps(XMMRegister dst, Operand src); void maxps(XMMRegister dst, XMMRegister src); - void maxps(XMMRegister dst, const Operand& src); + void maxps(XMMRegister dst, Operand src); void rcpps(XMMRegister dst, XMMRegister src); - void rcpps(XMMRegister dst, const Operand& src); + void rcpps(XMMRegister dst, Operand src); void rsqrtps(XMMRegister dst, XMMRegister src); - void rsqrtps(XMMRegister dst, const Operand& src); + void rsqrtps(XMMRegister dst, Operand src); void sqrtps(XMMRegister dst, XMMRegister src); - void sqrtps(XMMRegister dst, const Operand& src); + void sqrtps(XMMRegister dst, Operand src); void movups(XMMRegister dst, XMMRegister src); - void movups(XMMRegister dst, const Operand& src); - void movups(const Operand& dst, XMMRegister src); + void movups(XMMRegister dst, Operand src); + void movups(Operand dst, XMMRegister src); void psrldq(XMMRegister dst, uint8_t shift); void pshufd(XMMRegister dst, XMMRegister src, uint8_t shuffle); - void pshufd(XMMRegister dst, const Operand& src, uint8_t shuffle); + void pshufd(XMMRegister dst, Operand src, uint8_t shuffle); void pshufhw(XMMRegister dst, XMMRegister src, uint8_t shuffle); void pshuflw(XMMRegister dst, XMMRegister src, uint8_t shuffle); void cvtdq2ps(XMMRegister dst, XMMRegister src); - void cvtdq2ps(XMMRegister dst, const Operand& src); + void cvtdq2ps(XMMRegister dst, Operand src); // AVX instruction void vfmadd132sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { @@ -1294,13 +1275,13 @@ class Assembler : public AssemblerBase { void vfmadd231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { vfmasd(0xb9, dst, src1, src2); } - void vfmadd132sd(XMMRegister dst, XMMRegister src1, const Operand& src2) { + void vfmadd132sd(XMMRegister dst, XMMRegister src1, Operand src2) { vfmasd(0x99, dst, src1, src2); } - void vfmadd213sd(XMMRegister dst, XMMRegister src1, const Operand& src2) { + void vfmadd213sd(XMMRegister dst, XMMRegister src1, Operand src2) { vfmasd(0xa9, dst, src1, src2); } - void vfmadd231sd(XMMRegister dst, XMMRegister src1, const Operand& src2) { + void vfmadd231sd(XMMRegister dst, XMMRegister src1, Operand src2) { vfmasd(0xb9, dst, src1, src2); } void vfmsub132sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { @@ -1312,13 +1293,13 @@ class Assembler : public AssemblerBase { void vfmsub231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { vfmasd(0xbb, dst, src1, src2); } - void vfmsub132sd(XMMRegister dst, XMMRegister src1, const Operand& src2) { + void vfmsub132sd(XMMRegister dst, XMMRegister src1, Operand src2) { vfmasd(0x9b, dst, src1, src2); } - void vfmsub213sd(XMMRegister dst, XMMRegister src1, const Operand& src2) { + void vfmsub213sd(XMMRegister dst, XMMRegister src1, Operand src2) { vfmasd(0xab, dst, src1, src2); } - void vfmsub231sd(XMMRegister dst, XMMRegister src1, const Operand& src2) { + void vfmsub231sd(XMMRegister dst, XMMRegister src1, Operand src2) { vfmasd(0xbb, dst, src1, src2); } void vfnmadd132sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { @@ -1330,13 +1311,13 @@ class Assembler : public AssemblerBase { void vfnmadd231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { vfmasd(0xbd, dst, src1, src2); } - void vfnmadd132sd(XMMRegister dst, XMMRegister src1, const Operand& src2) { + void vfnmadd132sd(XMMRegister dst, XMMRegister src1, Operand src2) { vfmasd(0x9d, dst, src1, src2); } - void vfnmadd213sd(XMMRegister dst, XMMRegister src1, const Operand& src2) { + void vfnmadd213sd(XMMRegister dst, XMMRegister src1, Operand src2) { vfmasd(0xad, dst, src1, src2); } - void vfnmadd231sd(XMMRegister dst, XMMRegister src1, const Operand& src2) { + void vfnmadd231sd(XMMRegister dst, XMMRegister src1, Operand src2) { vfmasd(0xbd, dst, src1, src2); } void vfnmsub132sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { @@ -1348,17 +1329,17 @@ class Assembler : public AssemblerBase { void vfnmsub231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { vfmasd(0xbf, dst, src1, src2); } - void vfnmsub132sd(XMMRegister dst, XMMRegister src1, const Operand& src2) { + void vfnmsub132sd(XMMRegister dst, XMMRegister src1, Operand src2) { vfmasd(0x9f, dst, src1, src2); } - void vfnmsub213sd(XMMRegister dst, XMMRegister src1, const Operand& src2) { + void vfnmsub213sd(XMMRegister dst, XMMRegister src1, Operand src2) { vfmasd(0xaf, dst, src1, src2); } - void vfnmsub231sd(XMMRegister dst, XMMRegister src1, const Operand& src2) { + void vfnmsub231sd(XMMRegister dst, XMMRegister src1, Operand src2) { vfmasd(0xbf, dst, src1, src2); } void vfmasd(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2); - void vfmasd(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2); + void vfmasd(byte op, XMMRegister dst, XMMRegister src1, Operand src2); void vfmadd132ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) { vfmass(0x99, dst, src1, src2); @@ -1369,13 +1350,13 @@ class Assembler : public AssemblerBase { void vfmadd231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) { vfmass(0xb9, dst, src1, src2); } - void vfmadd132ss(XMMRegister dst, XMMRegister src1, const Operand& src2) { + void vfmadd132ss(XMMRegister dst, XMMRegister src1, Operand src2) { vfmass(0x99, dst, src1, src2); } - void vfmadd213ss(XMMRegister dst, XMMRegister src1, const Operand& src2) { + void vfmadd213ss(XMMRegister dst, XMMRegister src1, Operand src2) { vfmass(0xa9, dst, src1, src2); } - void vfmadd231ss(XMMRegister dst, XMMRegister src1, const Operand& src2) { + void vfmadd231ss(XMMRegister dst, XMMRegister src1, Operand src2) { vfmass(0xb9, dst, src1, src2); } void vfmsub132ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) { @@ -1387,13 +1368,13 @@ class Assembler : public AssemblerBase { void vfmsub231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) { vfmass(0xbb, dst, src1, src2); } - void vfmsub132ss(XMMRegister dst, XMMRegister src1, const Operand& src2) { + void vfmsub132ss(XMMRegister dst, XMMRegister src1, Operand src2) { vfmass(0x9b, dst, src1, src2); } - void vfmsub213ss(XMMRegister dst, XMMRegister src1, const Operand& src2) { + void vfmsub213ss(XMMRegister dst, XMMRegister src1, Operand src2) { vfmass(0xab, dst, src1, src2); } - void vfmsub231ss(XMMRegister dst, XMMRegister src1, const Operand& src2) { + void vfmsub231ss(XMMRegister dst, XMMRegister src1, Operand src2) { vfmass(0xbb, dst, src1, src2); } void vfnmadd132ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) { @@ -1405,13 +1386,13 @@ class Assembler : public AssemblerBase { void vfnmadd231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) { vfmass(0xbd, dst, src1, src2); } - void vfnmadd132ss(XMMRegister dst, XMMRegister src1, const Operand& src2) { + void vfnmadd132ss(XMMRegister dst, XMMRegister src1, Operand src2) { vfmass(0x9d, dst, src1, src2); } - void vfnmadd213ss(XMMRegister dst, XMMRegister src1, const Operand& src2) { + void vfnmadd213ss(XMMRegister dst, XMMRegister src1, Operand src2) { vfmass(0xad, dst, src1, src2); } - void vfnmadd231ss(XMMRegister dst, XMMRegister src1, const Operand& src2) { + void vfnmadd231ss(XMMRegister dst, XMMRegister src1, Operand src2) { vfmass(0xbd, dst, src1, src2); } void vfnmsub132ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) { @@ -1423,34 +1404,30 @@ class Assembler : public AssemblerBase { void vfnmsub231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) { vfmass(0xbf, dst, src1, src2); } - void vfnmsub132ss(XMMRegister dst, XMMRegister src1, const Operand& src2) { + void vfnmsub132ss(XMMRegister dst, XMMRegister src1, Operand src2) { vfmass(0x9f, dst, src1, src2); } - void vfnmsub213ss(XMMRegister dst, XMMRegister src1, const Operand& src2) { + void vfnmsub213ss(XMMRegister dst, XMMRegister src1, Operand src2) { vfmass(0xaf, dst, src1, src2); } - void vfnmsub231ss(XMMRegister dst, XMMRegister src1, const Operand& src2) { + void vfnmsub231ss(XMMRegister dst, XMMRegister src1, Operand src2) { vfmass(0xbf, dst, src1, src2); } void vfmass(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2); - void vfmass(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2); + void vfmass(byte op, XMMRegister dst, XMMRegister src1, Operand src2); void vmovd(XMMRegister dst, Register src); - void vmovd(XMMRegister dst, const Operand& src); + void vmovd(XMMRegister dst, Operand src); void vmovd(Register dst, XMMRegister src); void vmovq(XMMRegister dst, Register src); - void vmovq(XMMRegister dst, const Operand& src); + void vmovq(XMMRegister dst, Operand src); void vmovq(Register dst, XMMRegister src); void vmovsd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { vsd(0x10, dst, src1, src2); } - void vmovsd(XMMRegister dst, const Operand& src) { - vsd(0x10, dst, xmm0, src); - } - void vmovsd(const Operand& dst, XMMRegister src) { - vsd(0x11, src, xmm0, dst); - } + void vmovsd(XMMRegister dst, Operand src) { vsd(0x10, dst, xmm0, src); } + void vmovsd(Operand dst, XMMRegister src) { vsd(0x11, src, xmm0, dst); } #define AVX_SP_3(instr, opcode) \ AVX_S_3(instr, opcode) \ @@ -1464,12 +1441,12 @@ class Assembler : public AssemblerBase { AVX_3(instr##ps, opcode, vps) \ AVX_3(instr##pd, opcode, vpd) -#define AVX_3(instr, opcode, impl) \ - void instr(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \ - impl(opcode, dst, src1, src2); \ - } \ - void instr(XMMRegister dst, XMMRegister src1, const Operand& src2) { \ - impl(opcode, dst, src1, src2); \ +#define AVX_3(instr, opcode, impl) \ + void instr(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \ + impl(opcode, dst, src1, src2); \ + } \ + void instr(XMMRegister dst, XMMRegister src1, Operand src2) { \ + impl(opcode, dst, src1, src2); \ } AVX_SP_3(vsqrt, 0x51); @@ -1500,42 +1477,42 @@ class Assembler : public AssemblerBase { void vcvtss2sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { vinstr(0x5a, dst, src1, src2, kF3, k0F, kWIG); } - void vcvtss2sd(XMMRegister dst, XMMRegister src1, const Operand& src2) { + void vcvtss2sd(XMMRegister dst, XMMRegister src1, Operand src2) { vinstr(0x5a, dst, src1, src2, kF3, k0F, kWIG); } void vcvtlsi2sd(XMMRegister dst, XMMRegister src1, Register src2) { XMMRegister isrc2 = XMMRegister::from_code(src2.code()); vinstr(0x2a, dst, src1, isrc2, kF2, k0F, kW0); } - void vcvtlsi2sd(XMMRegister dst, XMMRegister src1, const Operand& src2) { + void vcvtlsi2sd(XMMRegister dst, XMMRegister src1, Operand src2) { vinstr(0x2a, dst, src1, src2, kF2, k0F, kW0); } void vcvtlsi2ss(XMMRegister dst, XMMRegister src1, Register src2) { XMMRegister isrc2 = XMMRegister::from_code(src2.code()); vinstr(0x2a, dst, src1, isrc2, kF3, k0F, kW0); } - void vcvtlsi2ss(XMMRegister dst, XMMRegister src1, const Operand& src2) { + void vcvtlsi2ss(XMMRegister dst, XMMRegister src1, Operand src2) { vinstr(0x2a, dst, src1, src2, kF3, k0F, kW0); } void vcvtqsi2ss(XMMRegister dst, XMMRegister src1, Register src2) { XMMRegister isrc2 = XMMRegister::from_code(src2.code()); vinstr(0x2a, dst, src1, isrc2, kF3, k0F, kW1); } - void vcvtqsi2ss(XMMRegister dst, XMMRegister src1, const Operand& src2) { + void vcvtqsi2ss(XMMRegister dst, XMMRegister src1, Operand src2) { vinstr(0x2a, dst, src1, src2, kF3, k0F, kW1); } void vcvtqsi2sd(XMMRegister dst, XMMRegister src1, Register src2) { XMMRegister isrc2 = XMMRegister::from_code(src2.code()); vinstr(0x2a, dst, src1, isrc2, kF2, k0F, kW1); } - void vcvtqsi2sd(XMMRegister dst, XMMRegister src1, const Operand& src2) { + void vcvtqsi2sd(XMMRegister dst, XMMRegister src1, Operand src2) { vinstr(0x2a, dst, src1, src2, kF2, k0F, kW1); } void vcvttss2si(Register dst, XMMRegister src) { XMMRegister idst = XMMRegister::from_code(dst.code()); vinstr(0x2c, idst, xmm0, src, kF3, k0F, kW0); } - void vcvttss2si(Register dst, const Operand& src) { + void vcvttss2si(Register dst, Operand src) { XMMRegister idst = XMMRegister::from_code(dst.code()); vinstr(0x2c, idst, xmm0, src, kF3, k0F, kW0); } @@ -1543,7 +1520,7 @@ class Assembler : public AssemblerBase { XMMRegister idst = XMMRegister::from_code(dst.code()); vinstr(0x2c, idst, xmm0, src, kF2, k0F, kW0); } - void vcvttsd2si(Register dst, const Operand& src) { + void vcvttsd2si(Register dst, Operand src) { XMMRegister idst = XMMRegister::from_code(dst.code()); vinstr(0x2c, idst, xmm0, src, kF2, k0F, kW0); } @@ -1551,7 +1528,7 @@ class Assembler : public AssemblerBase { XMMRegister idst = XMMRegister::from_code(dst.code()); vinstr(0x2c, idst, xmm0, src, kF3, k0F, kW1); } - void vcvttss2siq(Register dst, const Operand& src) { + void vcvttss2siq(Register dst, Operand src) { XMMRegister idst = XMMRegister::from_code(dst.code()); vinstr(0x2c, idst, xmm0, src, kF3, k0F, kW1); } @@ -1559,7 +1536,7 @@ class Assembler : public AssemblerBase { XMMRegister idst = XMMRegister::from_code(dst.code()); vinstr(0x2c, idst, xmm0, src, kF2, k0F, kW1); } - void vcvttsd2siq(Register dst, const Operand& src) { + void vcvttsd2siq(Register dst, Operand src) { XMMRegister idst = XMMRegister::from_code(dst.code()); vinstr(0x2c, idst, xmm0, src, kF2, k0F, kW1); } @@ -1570,7 +1547,7 @@ class Assembler : public AssemblerBase { void vucomisd(XMMRegister dst, XMMRegister src) { vinstr(0x2e, dst, xmm0, src, k66, k0F, kWIG); } - void vucomisd(XMMRegister dst, const Operand& src) { + void vucomisd(XMMRegister dst, Operand src) { vinstr(0x2e, dst, xmm0, src, k66, k0F, kWIG); } void vroundss(XMMRegister dst, XMMRegister src1, XMMRegister src2, @@ -1587,39 +1564,27 @@ class Assembler : public AssemblerBase { void vsd(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2) { vinstr(op, dst, src1, src2, kF2, k0F, kWIG); } - void vsd(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2) { + void vsd(byte op, XMMRegister dst, XMMRegister src1, Operand src2) { vinstr(op, dst, src1, src2, kF2, k0F, kWIG); } void vmovss(XMMRegister dst, XMMRegister src1, XMMRegister src2) { vss(0x10, dst, src1, src2); } - void vmovss(XMMRegister dst, const Operand& src) { - vss(0x10, dst, xmm0, src); - } - void vmovss(const Operand& dst, XMMRegister src) { - vss(0x11, src, xmm0, dst); - } + void vmovss(XMMRegister dst, Operand src) { vss(0x10, dst, xmm0, src); } + void vmovss(Operand dst, XMMRegister src) { vss(0x11, src, xmm0, dst); } void vucomiss(XMMRegister dst, XMMRegister src); - void vucomiss(XMMRegister dst, const Operand& src); + void vucomiss(XMMRegister dst, Operand src); void vss(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2); - void vss(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2); + void vss(byte op, XMMRegister dst, XMMRegister src1, Operand src2); void vmovaps(XMMRegister dst, XMMRegister src) { vps(0x28, dst, xmm0, src); } void vmovups(XMMRegister dst, XMMRegister src) { vps(0x10, dst, xmm0, src); } - void vmovups(XMMRegister dst, const Operand& src) { - vps(0x10, dst, xmm0, src); - } - void vmovups(const Operand& dst, XMMRegister src) { - vps(0x11, src, xmm0, dst); - } + void vmovups(XMMRegister dst, Operand src) { vps(0x10, dst, xmm0, src); } + void vmovups(Operand dst, XMMRegister src) { vps(0x11, src, xmm0, dst); } void vmovapd(XMMRegister dst, XMMRegister src) { vpd(0x28, dst, xmm0, src); } - void vmovupd(XMMRegister dst, const Operand& src) { - vpd(0x10, dst, xmm0, src); - } - void vmovupd(const Operand& dst, XMMRegister src) { - vpd(0x11, src, xmm0, dst); - } + void vmovupd(XMMRegister dst, Operand src) { vpd(0x10, dst, xmm0, src); } + void vmovupd(Operand dst, XMMRegister src) { vpd(0x11, src, xmm0, dst); } void vmovmskps(Register dst, XMMRegister src) { XMMRegister idst = XMMRegister::from_code(dst.code()); vps(0x50, idst, xmm0, src); @@ -1632,8 +1597,7 @@ class Assembler : public AssemblerBase { vps(0xC2, dst, src1, src2); emit(cmp); } - void vcmpps(XMMRegister dst, XMMRegister src1, const Operand& src2, - int8_t cmp) { + void vcmpps(XMMRegister dst, XMMRegister src1, Operand src2, int8_t cmp) { vps(0xC2, dst, src1, src2); emit(cmp); } @@ -1641,24 +1605,23 @@ class Assembler : public AssemblerBase { vpd(0xC2, dst, src1, src2); emit(cmp); } - void vcmppd(XMMRegister dst, XMMRegister src1, const Operand& src2, - int8_t cmp) { + void vcmppd(XMMRegister dst, XMMRegister src1, Operand src2, int8_t cmp) { vpd(0xC2, dst, src1, src2); emit(cmp); } -#define AVX_CMP_P(instr, imm8) \ - void instr##ps(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \ - vcmpps(dst, src1, src2, imm8); \ - } \ - void instr##ps(XMMRegister dst, XMMRegister src1, const Operand& src2) { \ - vcmpps(dst, src1, src2, imm8); \ - } \ - void instr##pd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \ - vcmppd(dst, src1, src2, imm8); \ - } \ - void instr##pd(XMMRegister dst, XMMRegister src1, const Operand& src2) { \ - vcmppd(dst, src1, src2, imm8); \ +#define AVX_CMP_P(instr, imm8) \ + void instr##ps(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \ + vcmpps(dst, src1, src2, imm8); \ + } \ + void instr##ps(XMMRegister dst, XMMRegister src1, Operand src2) { \ + vcmpps(dst, src1, src2, imm8); \ + } \ + void instr##pd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \ + vcmppd(dst, src1, src2, imm8); \ + } \ + void instr##pd(XMMRegister dst, XMMRegister src1, Operand src2) { \ + vcmppd(dst, src1, src2, imm8); \ } AVX_CMP_P(vcmpeq, 0x0); @@ -1670,7 +1633,7 @@ class Assembler : public AssemblerBase { #undef AVX_CMP_P - void vlddqu(XMMRegister dst, const Operand& src) { + void vlddqu(XMMRegister dst, Operand src) { vinstr(0xF0, dst, xmm0, src, kF2, k0F, kWIG); } void vpsllw(XMMRegister dst, XMMRegister src, int8_t imm8) { @@ -1702,7 +1665,7 @@ class Assembler : public AssemblerBase { vinstr(0x14, src, xmm0, idst, k66, k0F3A, kW0); emit(imm8); } - void vpextrb(const Operand& dst, XMMRegister src, int8_t imm8) { + void vpextrb(Operand dst, XMMRegister src, int8_t imm8) { vinstr(0x14, src, xmm0, dst, k66, k0F3A, kW0); emit(imm8); } @@ -1711,7 +1674,7 @@ class Assembler : public AssemblerBase { vinstr(0xc5, idst, xmm0, src, k66, k0F, kW0); emit(imm8); } - void vpextrw(const Operand& dst, XMMRegister src, int8_t imm8) { + void vpextrw(Operand dst, XMMRegister src, int8_t imm8) { vinstr(0x15, src, xmm0, dst, k66, k0F3A, kW0); emit(imm8); } @@ -1720,7 +1683,7 @@ class Assembler : public AssemblerBase { vinstr(0x16, src, xmm0, idst, k66, k0F3A, kW0); emit(imm8); } - void vpextrd(const Operand& dst, XMMRegister src, int8_t imm8) { + void vpextrd(Operand dst, XMMRegister src, int8_t imm8) { vinstr(0x16, src, xmm0, dst, k66, k0F3A, kW0); emit(imm8); } @@ -1729,8 +1692,7 @@ class Assembler : public AssemblerBase { vinstr(0x20, dst, src1, isrc, k66, k0F3A, kW0); emit(imm8); } - void vpinsrb(XMMRegister dst, XMMRegister src1, const Operand& src2, - int8_t imm8) { + void vpinsrb(XMMRegister dst, XMMRegister src1, Operand src2, int8_t imm8) { vinstr(0x20, dst, src1, src2, k66, k0F3A, kW0); emit(imm8); } @@ -1739,8 +1701,7 @@ class Assembler : public AssemblerBase { vinstr(0xc4, dst, src1, isrc, k66, k0F, kW0); emit(imm8); } - void vpinsrw(XMMRegister dst, XMMRegister src1, const Operand& src2, - int8_t imm8) { + void vpinsrw(XMMRegister dst, XMMRegister src1, Operand src2, int8_t imm8) { vinstr(0xc4, dst, src1, src2, k66, k0F, kW0); emit(imm8); } @@ -1749,8 +1710,7 @@ class Assembler : public AssemblerBase { vinstr(0x22, dst, src1, isrc, k66, k0F3A, kW0); emit(imm8); } - void vpinsrd(XMMRegister dst, XMMRegister src1, const Operand& src2, - int8_t imm8) { + void vpinsrd(XMMRegister dst, XMMRegister src1, Operand src2, int8_t imm8) { vinstr(0x22, dst, src1, src2, k66, k0F3A, kW0); emit(imm8); } @@ -1760,150 +1720,150 @@ class Assembler : public AssemblerBase { } void vps(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2); - void vps(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2); + void vps(byte op, XMMRegister dst, XMMRegister src1, Operand src2); void vpd(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2); - void vpd(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2); + void vpd(byte op, XMMRegister dst, XMMRegister src1, Operand src2); // BMI instruction void andnq(Register dst, Register src1, Register src2) { bmi1q(0xf2, dst, src1, src2); } - void andnq(Register dst, Register src1, const Operand& src2) { + void andnq(Register dst, Register src1, Operand src2) { bmi1q(0xf2, dst, src1, src2); } void andnl(Register dst, Register src1, Register src2) { bmi1l(0xf2, dst, src1, src2); } - void andnl(Register dst, Register src1, const Operand& src2) { + void andnl(Register dst, Register src1, Operand src2) { bmi1l(0xf2, dst, src1, src2); } void bextrq(Register dst, Register src1, Register src2) { bmi1q(0xf7, dst, src2, src1); } - void bextrq(Register dst, const Operand& src1, Register src2) { + void bextrq(Register dst, Operand src1, Register src2) { bmi1q(0xf7, dst, src2, src1); } void bextrl(Register dst, Register src1, Register src2) { bmi1l(0xf7, dst, src2, src1); } - void bextrl(Register dst, const Operand& src1, Register src2) { + void bextrl(Register dst, Operand src1, Register src2) { bmi1l(0xf7, dst, src2, src1); } void blsiq(Register dst, Register src) { bmi1q(0xf3, rbx, dst, src); } - void blsiq(Register dst, const Operand& src) { bmi1q(0xf3, rbx, dst, src); } + void blsiq(Register dst, Operand src) { bmi1q(0xf3, rbx, dst, src); } void blsil(Register dst, Register src) { bmi1l(0xf3, rbx, dst, src); } - void blsil(Register dst, const Operand& src) { bmi1l(0xf3, rbx, dst, src); } + void blsil(Register dst, Operand src) { bmi1l(0xf3, rbx, dst, src); } void blsmskq(Register dst, Register src) { bmi1q(0xf3, rdx, dst, src); } - void blsmskq(Register dst, const Operand& src) { bmi1q(0xf3, rdx, dst, src); } + void blsmskq(Register dst, Operand src) { bmi1q(0xf3, rdx, dst, src); } void blsmskl(Register dst, Register src) { bmi1l(0xf3, rdx, dst, src); } - void blsmskl(Register dst, const Operand& src) { bmi1l(0xf3, rdx, dst, src); } + void blsmskl(Register dst, Operand src) { bmi1l(0xf3, rdx, dst, src); } void blsrq(Register dst, Register src) { bmi1q(0xf3, rcx, dst, src); } - void blsrq(Register dst, const Operand& src) { bmi1q(0xf3, rcx, dst, src); } + void blsrq(Register dst, Operand src) { bmi1q(0xf3, rcx, dst, src); } void blsrl(Register dst, Register src) { bmi1l(0xf3, rcx, dst, src); } - void blsrl(Register dst, const Operand& src) { bmi1l(0xf3, rcx, dst, src); } + void blsrl(Register dst, Operand src) { bmi1l(0xf3, rcx, dst, src); } void tzcntq(Register dst, Register src); - void tzcntq(Register dst, const Operand& src); + void tzcntq(Register dst, Operand src); void tzcntl(Register dst, Register src); - void tzcntl(Register dst, const Operand& src); + void tzcntl(Register dst, Operand src); void lzcntq(Register dst, Register src); - void lzcntq(Register dst, const Operand& src); + void lzcntq(Register dst, Operand src); void lzcntl(Register dst, Register src); - void lzcntl(Register dst, const Operand& src); + void lzcntl(Register dst, Operand src); void popcntq(Register dst, Register src); - void popcntq(Register dst, const Operand& src); + void popcntq(Register dst, Operand src); void popcntl(Register dst, Register src); - void popcntl(Register dst, const Operand& src); + void popcntl(Register dst, Operand src); void bzhiq(Register dst, Register src1, Register src2) { bmi2q(kNone, 0xf5, dst, src2, src1); } - void bzhiq(Register dst, const Operand& src1, Register src2) { + void bzhiq(Register dst, Operand src1, Register src2) { bmi2q(kNone, 0xf5, dst, src2, src1); } void bzhil(Register dst, Register src1, Register src2) { bmi2l(kNone, 0xf5, dst, src2, src1); } - void bzhil(Register dst, const Operand& src1, Register src2) { + void bzhil(Register dst, Operand src1, Register src2) { bmi2l(kNone, 0xf5, dst, src2, src1); } void mulxq(Register dst1, Register dst2, Register src) { bmi2q(kF2, 0xf6, dst1, dst2, src); } - void mulxq(Register dst1, Register dst2, const Operand& src) { + void mulxq(Register dst1, Register dst2, Operand src) { bmi2q(kF2, 0xf6, dst1, dst2, src); } void mulxl(Register dst1, Register dst2, Register src) { bmi2l(kF2, 0xf6, dst1, dst2, src); } - void mulxl(Register dst1, Register dst2, const Operand& src) { + void mulxl(Register dst1, Register dst2, Operand src) { bmi2l(kF2, 0xf6, dst1, dst2, src); } void pdepq(Register dst, Register src1, Register src2) { bmi2q(kF2, 0xf5, dst, src1, src2); } - void pdepq(Register dst, Register src1, const Operand& src2) { + void pdepq(Register dst, Register src1, Operand src2) { bmi2q(kF2, 0xf5, dst, src1, src2); } void pdepl(Register dst, Register src1, Register src2) { bmi2l(kF2, 0xf5, dst, src1, src2); } - void pdepl(Register dst, Register src1, const Operand& src2) { + void pdepl(Register dst, Register src1, Operand src2) { bmi2l(kF2, 0xf5, dst, src1, src2); } void pextq(Register dst, Register src1, Register src2) { bmi2q(kF3, 0xf5, dst, src1, src2); } - void pextq(Register dst, Register src1, const Operand& src2) { + void pextq(Register dst, Register src1, Operand src2) { bmi2q(kF3, 0xf5, dst, src1, src2); } void pextl(Register dst, Register src1, Register src2) { bmi2l(kF3, 0xf5, dst, src1, src2); } - void pextl(Register dst, Register src1, const Operand& src2) { + void pextl(Register dst, Register src1, Operand src2) { bmi2l(kF3, 0xf5, dst, src1, src2); } void sarxq(Register dst, Register src1, Register src2) { bmi2q(kF3, 0xf7, dst, src2, src1); } - void sarxq(Register dst, const Operand& src1, Register src2) { + void sarxq(Register dst, Operand src1, Register src2) { bmi2q(kF3, 0xf7, dst, src2, src1); } void sarxl(Register dst, Register src1, Register src2) { bmi2l(kF3, 0xf7, dst, src2, src1); } - void sarxl(Register dst, const Operand& src1, Register src2) { + void sarxl(Register dst, Operand src1, Register src2) { bmi2l(kF3, 0xf7, dst, src2, src1); } void shlxq(Register dst, Register src1, Register src2) { bmi2q(k66, 0xf7, dst, src2, src1); } - void shlxq(Register dst, const Operand& src1, Register src2) { + void shlxq(Register dst, Operand src1, Register src2) { bmi2q(k66, 0xf7, dst, src2, src1); } void shlxl(Register dst, Register src1, Register src2) { bmi2l(k66, 0xf7, dst, src2, src1); } - void shlxl(Register dst, const Operand& src1, Register src2) { + void shlxl(Register dst, Operand src1, Register src2) { bmi2l(k66, 0xf7, dst, src2, src1); } void shrxq(Register dst, Register src1, Register src2) { bmi2q(kF2, 0xf7, dst, src2, src1); } - void shrxq(Register dst, const Operand& src1, Register src2) { + void shrxq(Register dst, Operand src1, Register src2) { bmi2q(kF2, 0xf7, dst, src2, src1); } void shrxl(Register dst, Register src1, Register src2) { bmi2l(kF2, 0xf7, dst, src2, src1); } - void shrxl(Register dst, const Operand& src1, Register src2) { + void shrxl(Register dst, Operand src1, Register src2) { bmi2l(kF2, 0xf7, dst, src2, src1); } void rorxq(Register dst, Register src, byte imm8); - void rorxq(Register dst, const Operand& src, byte imm8); + void rorxq(Register dst, Operand src, byte imm8); void rorxl(Register dst, Register src, byte imm8); - void rorxl(Register dst, const Operand& src, byte imm8); + void rorxl(Register dst, Operand src, byte imm8); void lfence(); void pause(); @@ -1961,7 +1921,7 @@ class Assembler : public AssemblerBase { protected: // Call near indirect - void call(const Operand& operand); + void call(Operand operand); private: byte* addr_at(int pos) { return buffer_ + pos; } @@ -1997,8 +1957,8 @@ class Assembler : public AssemblerBase { // The high bit of reg is used for REX.R, the high bit of op's base // register is used for REX.B, and the high bit of op's index register // is used for REX.X. REX.W is set. - inline void emit_rex_64(Register reg, const Operand& op); - inline void emit_rex_64(XMMRegister reg, const Operand& op); + inline void emit_rex_64(Register reg, Operand op); + inline void emit_rex_64(XMMRegister reg, Operand op); // Emits a REX prefix that encodes a 64-bit operand size and // the top bit of the register code. @@ -2011,7 +1971,7 @@ class Assembler : public AssemblerBase { // The high bit of op's base register is used for REX.B, and the high // bit of op's index register is used for REX.X. // REX.W is set and REX.R clear. - inline void emit_rex_64(const Operand& op); + inline void emit_rex_64(Operand op); // Emit a REX prefix that only sets REX.W to choose a 64-bit operand size. void emit_rex_64() { emit(0x48); } @@ -2023,7 +1983,7 @@ class Assembler : public AssemblerBase { // The high bit of reg is used for REX.R, the high bit of op's base // register is used for REX.B, and the high bit of op's index register // is used for REX.X. REX.W is cleared. - inline void emit_rex_32(Register reg, const Operand& op); + inline void emit_rex_32(Register reg, Operand op); // High bit of rm_reg goes to REX.B. // REX.W, REX.R and REX.X are clear. @@ -2031,7 +1991,7 @@ class Assembler : public AssemblerBase { // High bit of base goes to REX.B and high bit of index to REX.X. // REX.W and REX.R are clear. - inline void emit_rex_32(const Operand& op); + inline void emit_rex_32(Operand op); // High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B. // REX.W is cleared. If no REX bits are set, no byte is emitted. @@ -2041,7 +2001,7 @@ class Assembler : public AssemblerBase { // register is used for REX.B, and the high bit of op's index register // is used for REX.X. REX.W is cleared. If no REX bits are set, nothing // is emitted. - inline void emit_optional_rex_32(Register reg, const Operand& op); + inline void emit_optional_rex_32(Register reg, Operand op); // As for emit_optional_rex_32(Register, Register), except that // the registers are XMM registers. @@ -2055,18 +2015,18 @@ class Assembler : public AssemblerBase { // one of the registers is an XMM registers. inline void emit_optional_rex_32(Register reg, XMMRegister base); - // As for emit_optional_rex_32(Register, const Operand&), except that + // As for emit_optional_rex_32(Register, Operand), except that // the register is an XMM register. - inline void emit_optional_rex_32(XMMRegister reg, const Operand& op); + inline void emit_optional_rex_32(XMMRegister reg, Operand op); // Optionally do as emit_rex_32(Register) if the register number has // the high bit set. inline void emit_optional_rex_32(Register rm_reg); inline void emit_optional_rex_32(XMMRegister rm_reg); - // Optionally do as emit_rex_32(const Operand&) if the operand register + // Optionally do as emit_rex_32(Operand) if the operand register // numbers have a high bit set. - inline void emit_optional_rex_32(const Operand& op); + inline void emit_optional_rex_32(Operand op); void emit_rex(int size) { if (size == kInt64Size) { @@ -2102,8 +2062,7 @@ class Assembler : public AssemblerBase { SIMDPrefix pp); void emit_vex3_byte0() { emit(0xc4); } inline void emit_vex3_byte1(XMMRegister reg, XMMRegister rm, LeadingOpcode m); - inline void emit_vex3_byte1(XMMRegister reg, const Operand& rm, - LeadingOpcode m); + inline void emit_vex3_byte1(XMMRegister reg, Operand rm, LeadingOpcode m); inline void emit_vex3_byte2(VexW w, XMMRegister v, VectorLength l, SIMDPrefix pp); inline void emit_vex_prefix(XMMRegister reg, XMMRegister v, XMMRegister rm, @@ -2112,10 +2071,10 @@ class Assembler : public AssemblerBase { inline void emit_vex_prefix(Register reg, Register v, Register rm, VectorLength l, SIMDPrefix pp, LeadingOpcode m, VexW w); - inline void emit_vex_prefix(XMMRegister reg, XMMRegister v, const Operand& rm, + inline void emit_vex_prefix(XMMRegister reg, XMMRegister v, Operand rm, VectorLength l, SIMDPrefix pp, LeadingOpcode m, VexW w); - inline void emit_vex_prefix(Register reg, Register v, const Operand& rm, + inline void emit_vex_prefix(Register reg, Register v, Operand rm, VectorLength l, SIMDPrefix pp, LeadingOpcode m, VexW w); @@ -2123,14 +2082,14 @@ class Assembler : public AssemblerBase { // 1- or 4-byte offset for a memory operand. Also encodes // the second operand of the operation, a register or operation // subcode, into the reg field of the ModR/M byte. - void emit_operand(Register reg, const Operand& adr) { + void emit_operand(Register reg, Operand adr) { emit_operand(reg.low_bits(), adr); } // Emit the ModR/M byte, and optionally the SIB byte and // 1- or 4-byte offset for a memory operand. Also used to encode // a three-bit opcode extension into the ModR/M byte. - void emit_operand(int rm, const Operand& adr); + void emit_operand(int rm, Operand adr); // Emit a ModR/M byte with registers coded in the reg and rm_reg fields. void emit_modrm(Register reg, Register rm_reg) { @@ -2149,8 +2108,8 @@ class Assembler : public AssemblerBase { // The first argument is the reg field, the second argument is the r/m field. void emit_sse_operand(XMMRegister dst, XMMRegister src); - void emit_sse_operand(XMMRegister reg, const Operand& adr); - void emit_sse_operand(Register reg, const Operand& adr); + void emit_sse_operand(XMMRegister reg, Operand adr); + void emit_sse_operand(Register reg, Operand adr); void emit_sse_operand(XMMRegister dst, Register src); void emit_sse_operand(Register dst, XMMRegister src); void emit_sse_operand(XMMRegister dst); @@ -2160,37 +2119,28 @@ class Assembler : public AssemblerBase { // similar, differing just in the opcode or in the reg field of the // ModR/M byte. void arithmetic_op_8(byte opcode, Register reg, Register rm_reg); - void arithmetic_op_8(byte opcode, Register reg, const Operand& rm_reg); + void arithmetic_op_8(byte opcode, Register reg, Operand rm_reg); void arithmetic_op_16(byte opcode, Register reg, Register rm_reg); - void arithmetic_op_16(byte opcode, Register reg, const Operand& rm_reg); + void arithmetic_op_16(byte opcode, Register reg, Operand rm_reg); // Operate on operands/registers with pointer size, 32-bit or 64-bit size. void arithmetic_op(byte opcode, Register reg, Register rm_reg, int size); - void arithmetic_op(byte opcode, - Register reg, - const Operand& rm_reg, - int size); + void arithmetic_op(byte opcode, Register reg, Operand rm_reg, int size); // Operate on a byte in memory or register. void immediate_arithmetic_op_8(byte subcode, Register dst, Immediate src); - void immediate_arithmetic_op_8(byte subcode, - const Operand& dst, - Immediate src); + void immediate_arithmetic_op_8(byte subcode, Operand dst, Immediate src); // Operate on a word in memory or register. void immediate_arithmetic_op_16(byte subcode, Register dst, Immediate src); - void immediate_arithmetic_op_16(byte subcode, - const Operand& dst, - Immediate src); + void immediate_arithmetic_op_16(byte subcode, Operand dst, Immediate src); // Operate on operands/registers with pointer size, 32-bit or 64-bit size. void immediate_arithmetic_op(byte subcode, Register dst, Immediate src, int size); - void immediate_arithmetic_op(byte subcode, - const Operand& dst, - Immediate src, + void immediate_arithmetic_op(byte subcode, Operand dst, Immediate src, int size); // Emit machine code for a shift operation. @@ -2218,15 +2168,15 @@ class Assembler : public AssemblerBase { immediate_arithmetic_op(0x0, dst, src, size); } - void emit_add(Register dst, const Operand& src, int size) { + void emit_add(Register dst, Operand src, int size) { arithmetic_op(0x03, dst, src, size); } - void emit_add(const Operand& dst, Register src, int size) { + void emit_add(Operand dst, Register src, int size) { arithmetic_op(0x1, src, dst, size); } - void emit_add(const Operand& dst, Immediate src, int size) { + void emit_add(Operand dst, Immediate src, int size) { immediate_arithmetic_op(0x0, dst, src, size); } @@ -2234,11 +2184,11 @@ class Assembler : public AssemblerBase { arithmetic_op(0x23, dst, src, size); } - void emit_and(Register dst, const Operand& src, int size) { + void emit_and(Register dst, Operand src, int size) { arithmetic_op(0x23, dst, src, size); } - void emit_and(const Operand& dst, Register src, int size) { + void emit_and(Operand dst, Register src, int size) { arithmetic_op(0x21, src, dst, size); } @@ -2246,7 +2196,7 @@ class Assembler : public AssemblerBase { immediate_arithmetic_op(0x4, dst, src, size); } - void emit_and(const Operand& dst, Immediate src, int size) { + void emit_and(Operand dst, Immediate src, int size) { immediate_arithmetic_op(0x4, dst, src, size); } @@ -2254,11 +2204,11 @@ class Assembler : public AssemblerBase { arithmetic_op(0x3B, dst, src, size); } - void emit_cmp(Register dst, const Operand& src, int size) { + void emit_cmp(Register dst, Operand src, int size) { arithmetic_op(0x3B, dst, src, size); } - void emit_cmp(const Operand& dst, Register src, int size) { + void emit_cmp(Operand dst, Register src, int size) { arithmetic_op(0x39, src, dst, size); } @@ -2266,17 +2216,17 @@ class Assembler : public AssemblerBase { immediate_arithmetic_op(0x7, dst, src, size); } - void emit_cmp(const Operand& dst, Immediate src, int size) { + void emit_cmp(Operand dst, Immediate src, int size) { immediate_arithmetic_op(0x7, dst, src, size); } // Compare {al,ax,eax,rax} with src. If equal, set ZF and write dst into // src. Otherwise clear ZF and write src into {al,ax,eax,rax}. This // operation is only atomic if prefixed by the lock instruction. - void emit_cmpxchg(const Operand& dst, Register src, int size); + void emit_cmpxchg(Operand dst, Register src, int size); void emit_dec(Register dst, int size); - void emit_dec(const Operand& dst, int size); + void emit_dec(Operand dst, int size); // Divide rdx:rax by src. Quotient in rax, remainder in rdx when size is 64. // Divide edx:eax by lower 32 bits of src. Quotient in eax, remainder in edx @@ -2287,43 +2237,43 @@ class Assembler : public AssemblerBase { // Signed multiply instructions. // rdx:rax = rax * src when size is 64 or edx:eax = eax * src when size is 32. void emit_imul(Register src, int size); - void emit_imul(const Operand& src, int size); + void emit_imul(Operand src, int size); void emit_imul(Register dst, Register src, int size); - void emit_imul(Register dst, const Operand& src, int size); + void emit_imul(Register dst, Operand src, int size); void emit_imul(Register dst, Register src, Immediate imm, int size); - void emit_imul(Register dst, const Operand& src, Immediate imm, int size); + void emit_imul(Register dst, Operand src, Immediate imm, int size); void emit_inc(Register dst, int size); - void emit_inc(const Operand& dst, int size); + void emit_inc(Operand dst, int size); - void emit_lea(Register dst, const Operand& src, int size); + void emit_lea(Register dst, Operand src, int size); - void emit_mov(Register dst, const Operand& src, int size); + void emit_mov(Register dst, Operand src, int size); void emit_mov(Register dst, Register src, int size); - void emit_mov(const Operand& dst, Register src, int size); + void emit_mov(Operand dst, Register src, int size); void emit_mov(Register dst, Immediate value, int size); - void emit_mov(const Operand& dst, Immediate value, int size); + void emit_mov(Operand dst, Immediate value, int size); - void emit_movzxb(Register dst, const Operand& src, int size); + void emit_movzxb(Register dst, Operand src, int size); void emit_movzxb(Register dst, Register src, int size); - void emit_movzxw(Register dst, const Operand& src, int size); + void emit_movzxw(Register dst, Operand src, int size); void emit_movzxw(Register dst, Register src, int size); void emit_neg(Register dst, int size); - void emit_neg(const Operand& dst, int size); + void emit_neg(Operand dst, int size); void emit_not(Register dst, int size); - void emit_not(const Operand& dst, int size); + void emit_not(Operand dst, int size); void emit_or(Register dst, Register src, int size) { arithmetic_op(0x0B, dst, src, size); } - void emit_or(Register dst, const Operand& src, int size) { + void emit_or(Register dst, Operand src, int size) { arithmetic_op(0x0B, dst, src, size); } - void emit_or(const Operand& dst, Register src, int size) { + void emit_or(Operand dst, Register src, int size) { arithmetic_op(0x9, src, dst, size); } @@ -2331,7 +2281,7 @@ class Assembler : public AssemblerBase { immediate_arithmetic_op(0x1, dst, src, size); } - void emit_or(const Operand& dst, Immediate src, int size) { + void emit_or(Operand dst, Immediate src, int size) { immediate_arithmetic_op(0x1, dst, src, size); } @@ -2349,28 +2299,28 @@ class Assembler : public AssemblerBase { immediate_arithmetic_op(0x5, dst, src, size); } - void emit_sub(Register dst, const Operand& src, int size) { + void emit_sub(Register dst, Operand src, int size) { arithmetic_op(0x2B, dst, src, size); } - void emit_sub(const Operand& dst, Register src, int size) { + void emit_sub(Operand dst, Register src, int size) { arithmetic_op(0x29, src, dst, size); } - void emit_sub(const Operand& dst, Immediate src, int size) { + void emit_sub(Operand dst, Immediate src, int size) { immediate_arithmetic_op(0x5, dst, src, size); } void emit_test(Register dst, Register src, int size); void emit_test(Register reg, Immediate mask, int size); - void emit_test(const Operand& op, Register reg, int size); - void emit_test(const Operand& op, Immediate mask, int size); - void emit_test(Register reg, const Operand& op, int size) { + void emit_test(Operand op, Register reg, int size); + void emit_test(Operand op, Immediate mask, int size); + void emit_test(Register reg, Operand op, int size) { return emit_test(op, reg, size); } void emit_xchg(Register dst, Register src, int size); - void emit_xchg(Register dst, const Operand& src, int size); + void emit_xchg(Register dst, Operand src, int size); void emit_xor(Register dst, Register src, int size) { if (size == kInt64Size && dst.code() == src.code()) { @@ -2382,7 +2332,7 @@ class Assembler : public AssemblerBase { } } - void emit_xor(Register dst, const Operand& src, int size) { + void emit_xor(Register dst, Operand src, int size) { arithmetic_op(0x33, dst, src, size); } @@ -2390,25 +2340,23 @@ class Assembler : public AssemblerBase { immediate_arithmetic_op(0x6, dst, src, size); } - void emit_xor(const Operand& dst, Immediate src, int size) { + void emit_xor(Operand dst, Immediate src, int size) { immediate_arithmetic_op(0x6, dst, src, size); } - void emit_xor(const Operand& dst, Register src, int size) { + void emit_xor(Operand dst, Register src, int size) { arithmetic_op(0x31, src, dst, size); } // Most BMI instructions are similar. void bmi1q(byte op, Register reg, Register vreg, Register rm); - void bmi1q(byte op, Register reg, Register vreg, const Operand& rm); + void bmi1q(byte op, Register reg, Register vreg, Operand rm); void bmi1l(byte op, Register reg, Register vreg, Register rm); - void bmi1l(byte op, Register reg, Register vreg, const Operand& rm); + void bmi1l(byte op, Register reg, Register vreg, Operand rm); void bmi2q(SIMDPrefix pp, byte op, Register reg, Register vreg, Register rm); - void bmi2q(SIMDPrefix pp, byte op, Register reg, Register vreg, - const Operand& rm); + void bmi2q(SIMDPrefix pp, byte op, Register reg, Register vreg, Operand rm); void bmi2l(SIMDPrefix pp, byte op, Register reg, Register vreg, Register rm); - void bmi2l(SIMDPrefix pp, byte op, Register reg, Register vreg, - const Operand& rm); + void bmi2l(SIMDPrefix pp, byte op, Register reg, Register vreg, Operand rm); // record the position of jmp/jcc instruction void record_farjmp_position(Label* L, int pos); |