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Diffstat (limited to 'deps/v8/src/x64/assembler-x64.cc')
-rw-r--r--deps/v8/src/x64/assembler-x64.cc137
1 files changed, 83 insertions, 54 deletions
diff --git a/deps/v8/src/x64/assembler-x64.cc b/deps/v8/src/x64/assembler-x64.cc
index 5f62e2af66..38cbfc78d9 100644
--- a/deps/v8/src/x64/assembler-x64.cc
+++ b/deps/v8/src/x64/assembler-x64.cc
@@ -38,7 +38,7 @@ V8_INLINE uint64_t _xgetbv(unsigned int xcr) {
// directly because older assemblers do not include support for xgetbv and
// there is no easy way to conditionally compile based on the assembler
// used.
- __asm__ volatile(".byte 0x0f, 0x01, 0xd0" : "=a"(eax), "=d"(edx) : "c"(xcr));
+ __asm__ volatile(".byte 0x0F, 0x01, 0xD0" : "=a"(eax), "=d"(edx) : "c"(xcr));
return static_cast<uint64_t>(eax) | (static_cast<uint64_t>(edx) << 32);
}
@@ -243,17 +243,17 @@ Operand::Operand(const Operand& operand, int32_t offset) {
rex_ = operand.rex_;
if (!is_int8(disp_value) || is_baseless) {
// Need 32 bits of displacement, mode 2 or mode 1 with register rbp/r13.
- buf_[0] = (modrm & 0x3f) | (is_baseless ? 0x00 : 0x80);
+ buf_[0] = (modrm & 0x3F) | (is_baseless ? 0x00 : 0x80);
len_ = disp_offset + 4;
Memory::int32_at(&buf_[disp_offset]) = disp_value;
} else if (disp_value != 0 || (base_reg == 0x05)) {
// Need 8 bits of displacement.
- buf_[0] = (modrm & 0x3f) | 0x40; // Mode 1.
+ buf_[0] = (modrm & 0x3F) | 0x40; // Mode 1.
len_ = disp_offset + 1;
buf_[disp_offset] = static_cast<byte>(disp_value);
} else {
// Need no displacement.
- buf_[0] = (modrm & 0x3f); // Mode 0.
+ buf_[0] = (modrm & 0x3F); // Mode 0.
len_ = disp_offset;
}
if (has_sib) {
@@ -385,7 +385,7 @@ bool Assembler::IsNop(Address addr) {
Address a = addr;
while (*a == 0x66) a++;
if (*a == 0x90) return true;
- if (a[0] == 0xf && a[1] == 0x1f) return true;
+ if (a[0] == 0xF && a[1] == 0x1F) return true;
return false;
}
@@ -1044,7 +1044,7 @@ void Assembler::cmovq(Condition cc, Register dst, Register src) {
EnsureSpace ensure_space(this);
// Opcode: REX.W 0f 40 + cc /r.
emit_rex_64(dst, src);
- emit(0x0f);
+ emit(0x0F);
emit(0x40 + cc);
emit_modrm(dst, src);
}
@@ -1060,7 +1060,7 @@ void Assembler::cmovq(Condition cc, Register dst, const Operand& src) {
EnsureSpace ensure_space(this);
// Opcode: REX.W 0f 40 + cc /r.
emit_rex_64(dst, src);
- emit(0x0f);
+ emit(0x0F);
emit(0x40 + cc);
emit_operand(dst, src);
}
@@ -1076,7 +1076,7 @@ void Assembler::cmovl(Condition cc, Register dst, Register src) {
EnsureSpace ensure_space(this);
// Opcode: 0f 40 + cc /r.
emit_optional_rex_32(dst, src);
- emit(0x0f);
+ emit(0x0F);
emit(0x40 + cc);
emit_modrm(dst, src);
}
@@ -1092,7 +1092,7 @@ void Assembler::cmovl(Condition cc, Register dst, const Operand& src) {
EnsureSpace ensure_space(this);
// Opcode: 0f 40 + cc /r.
emit_optional_rex_32(dst, src);
- emit(0x0f);
+ emit(0x0F);
emit(0x40 + cc);
emit_operand(dst, src);
}
@@ -1101,13 +1101,13 @@ void Assembler::cmovl(Condition cc, Register dst, const Operand& src) {
void Assembler::cmpb_al(Immediate imm8) {
DCHECK(is_int8(imm8.value_) || is_uint8(imm8.value_));
EnsureSpace ensure_space(this);
- emit(0x3c);
+ emit(0x3C);
emit(imm8.value_);
}
void Assembler::lock() {
EnsureSpace ensure_space(this);
- emit(0xf0);
+ emit(0xF0);
}
void Assembler::cmpxchgb(const Operand& dst, Register src) {
@@ -1118,8 +1118,8 @@ void Assembler::cmpxchgb(const Operand& dst, Register src) {
} else {
emit_optional_rex_32(src, dst);
}
- emit(0x0f);
- emit(0xb0);
+ emit(0x0F);
+ emit(0xB0);
emit_operand(src, dst);
}
@@ -1127,19 +1127,26 @@ void Assembler::cmpxchgw(const Operand& dst, Register src) {
EnsureSpace ensure_space(this);
emit(0x66);
emit_optional_rex_32(src, dst);
- emit(0x0f);
- emit(0xb1);
+ emit(0x0F);
+ emit(0xB1);
emit_operand(src, dst);
}
void Assembler::emit_cmpxchg(const Operand& dst, Register src, int size) {
EnsureSpace ensure_space(this);
emit_rex(src, dst, size);
- emit(0x0f);
- emit(0xb1);
+ emit(0x0F);
+ emit(0xB1);
emit_operand(src, dst);
}
+void Assembler::lfence() {
+ EnsureSpace ensure_space(this);
+ emit(0x0F);
+ emit(0xAE);
+ emit(0xE8);
+}
+
void Assembler::cpuid() {
EnsureSpace ensure_space(this);
emit(0x0F);
@@ -1593,7 +1600,7 @@ void Assembler::movw(const Operand& dst, Immediate imm) {
emit_optional_rex_32(dst);
emit(0xC7);
emit_operand(0x0, dst);
- emit(static_cast<byte>(imm.value_ & 0xff));
+ emit(static_cast<byte>(imm.value_ & 0xFF));
emit(static_cast<byte>(imm.value_ >> 8));
}
@@ -1950,28 +1957,28 @@ void Assembler::Nop(int n) {
emit(0x90);
return;
case 3:
- emit(0x0f);
- emit(0x1f);
+ emit(0x0F);
+ emit(0x1F);
emit(0x00);
return;
case 4:
- emit(0x0f);
- emit(0x1f);
+ emit(0x0F);
+ emit(0x1F);
emit(0x40);
emit(0x00);
return;
case 6:
emit(0x66);
case 5:
- emit(0x0f);
- emit(0x1f);
+ emit(0x0F);
+ emit(0x1F);
emit(0x44);
emit(0x00);
emit(0x00);
return;
case 7:
- emit(0x0f);
- emit(0x1f);
+ emit(0x0F);
+ emit(0x1F);
emit(0x80);
emit(0x00);
emit(0x00);
@@ -1989,8 +1996,8 @@ void Assembler::Nop(int n) {
emit(0x66);
n--;
case 8:
- emit(0x0f);
- emit(0x1f);
+ emit(0x0F);
+ emit(0x1F);
emit(0x84);
emit(0x00);
emit(0x00);
@@ -2898,10 +2905,10 @@ void Assembler::movq(XMMRegister dst, XMMRegister src) {
EnsureSpace ensure_space(this);
if (dst.low_bits() == 4) {
// Avoid unnecessary SIB byte.
- emit(0xf3);
+ emit(0xF3);
emit_optional_rex_32(dst, src);
emit(0x0F);
- emit(0x7e);
+ emit(0x7E);
emit_sse_operand(dst, src);
} else {
emit(0x66);
@@ -3370,8 +3377,8 @@ void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
DCHECK(!IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
- emit(0x0f);
- emit(0x2e);
+ emit(0x0F);
+ emit(0x2E);
emit_sse_operand(dst, src);
}
@@ -3380,8 +3387,8 @@ void Assembler::ucomiss(XMMRegister dst, const Operand& src) {
DCHECK(!IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
- emit(0x0f);
- emit(0x2e);
+ emit(0x0F);
+ emit(0x2E);
emit_sse_operand(dst, src);
}
@@ -3984,14 +3991,31 @@ void Assembler::sqrtsd(XMMRegister dst, const Operand& src) {
emit_sse_operand(dst, src);
}
+void Assembler::haddps(XMMRegister dst, XMMRegister src) {
+ EnsureSpace ensure_space(this);
+ emit(0xF2);
+ emit_optional_rex_32(dst, src);
+ emit(0x0F);
+ emit(0x7C);
+ emit_sse_operand(dst, src);
+}
+
+void Assembler::haddps(XMMRegister dst, const Operand& src) {
+ EnsureSpace ensure_space(this);
+ emit(0xF2);
+ emit_optional_rex_32(dst, src);
+ emit(0x0F);
+ emit(0x7C);
+ emit_sse_operand(dst, src);
+}
void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
DCHECK(!IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit(0x66);
emit_optional_rex_32(dst, src);
- emit(0x0f);
- emit(0x2e);
+ emit(0x0F);
+ emit(0x2E);
emit_sse_operand(dst, src);
}
@@ -4001,8 +4025,8 @@ void Assembler::ucomisd(XMMRegister dst, const Operand& src) {
EnsureSpace ensure_space(this);
emit(0x66);
emit_optional_rex_32(dst, src);
- emit(0x0f);
- emit(0x2e);
+ emit(0x0F);
+ emit(0x2E);
emit_sse_operand(dst, src);
}
@@ -4024,9 +4048,9 @@ void Assembler::roundss(XMMRegister dst, XMMRegister src, RoundingMode mode) {
EnsureSpace ensure_space(this);
emit(0x66);
emit_optional_rex_32(dst, src);
- emit(0x0f);
- emit(0x3a);
- emit(0x0a);
+ emit(0x0F);
+ emit(0x3A);
+ emit(0x0A);
emit_sse_operand(dst, src);
// Mask precision exception.
emit(static_cast<byte>(mode) | 0x8);
@@ -4039,9 +4063,9 @@ void Assembler::roundsd(XMMRegister dst, XMMRegister src, RoundingMode mode) {
EnsureSpace ensure_space(this);
emit(0x66);
emit_optional_rex_32(dst, src);
- emit(0x0f);
- emit(0x3a);
- emit(0x0b);
+ emit(0x0F);
+ emit(0x3A);
+ emit(0x0B);
emit_sse_operand(dst, src);
// Mask precision exception.
emit(static_cast<byte>(mode) | 0x8);
@@ -4052,7 +4076,7 @@ void Assembler::movmskpd(Register dst, XMMRegister src) {
EnsureSpace ensure_space(this);
emit(0x66);
emit_optional_rex_32(dst, src);
- emit(0x0f);
+ emit(0x0F);
emit(0x50);
emit_sse_operand(dst, src);
}
@@ -4061,7 +4085,7 @@ void Assembler::movmskpd(Register dst, XMMRegister src) {
void Assembler::movmskps(Register dst, XMMRegister src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
- emit(0x0f);
+ emit(0x0F);
emit(0x50);
emit_sse_operand(dst, src);
}
@@ -4141,7 +4165,7 @@ void Assembler::vmovd(XMMRegister dst, Register src) {
EnsureSpace ensure_space(this);
XMMRegister isrc = XMMRegister::from_code(src.code());
emit_vex_prefix(dst, xmm0, isrc, kL128, k66, k0F, kW0);
- emit(0x6e);
+ emit(0x6E);
emit_sse_operand(dst, src);
}
@@ -4150,7 +4174,7 @@ void Assembler::vmovd(XMMRegister dst, const Operand& src) {
DCHECK(IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit_vex_prefix(dst, xmm0, src, kL128, k66, k0F, kW0);
- emit(0x6e);
+ emit(0x6E);
emit_sse_operand(dst, src);
}
@@ -4160,7 +4184,7 @@ void Assembler::vmovd(Register dst, XMMRegister src) {
EnsureSpace ensure_space(this);
XMMRegister idst = XMMRegister::from_code(dst.code());
emit_vex_prefix(src, xmm0, idst, kL128, k66, k0F, kW0);
- emit(0x7e);
+ emit(0x7E);
emit_sse_operand(src, dst);
}
@@ -4170,7 +4194,7 @@ void Assembler::vmovq(XMMRegister dst, Register src) {
EnsureSpace ensure_space(this);
XMMRegister isrc = XMMRegister::from_code(src.code());
emit_vex_prefix(dst, xmm0, isrc, kL128, k66, k0F, kW1);
- emit(0x6e);
+ emit(0x6E);
emit_sse_operand(dst, src);
}
@@ -4179,7 +4203,7 @@ void Assembler::vmovq(XMMRegister dst, const Operand& src) {
DCHECK(IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit_vex_prefix(dst, xmm0, src, kL128, k66, k0F, kW1);
- emit(0x6e);
+ emit(0x6E);
emit_sse_operand(dst, src);
}
@@ -4189,7 +4213,7 @@ void Assembler::vmovq(Register dst, XMMRegister src) {
EnsureSpace ensure_space(this);
XMMRegister idst = XMMRegister::from_code(dst.code());
emit_vex_prefix(src, xmm0, idst, kL128, k66, k0F, kW1);
- emit(0x7e);
+ emit(0x7E);
emit_sse_operand(src, dst);
}
@@ -4258,7 +4282,7 @@ void Assembler::vucomiss(XMMRegister dst, XMMRegister src) {
DCHECK(IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit_vex_prefix(dst, xmm0, src, kLIG, kNone, k0F, kWIG);
- emit(0x2e);
+ emit(0x2E);
emit_sse_operand(dst, src);
}
@@ -4267,7 +4291,7 @@ void Assembler::vucomiss(XMMRegister dst, const Operand& src) {
DCHECK(IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit_vex_prefix(dst, xmm0, src, kLIG, kNone, k0F, kWIG);
- emit(0x2e);
+ emit(0x2E);
emit_sse_operand(dst, src);
}
@@ -4547,6 +4571,11 @@ void Assembler::rorxl(Register dst, const Operand& src, byte imm8) {
emit(imm8);
}
+void Assembler::pause() {
+ emit(0xF3);
+ emit(0x90);
+}
+
void Assembler::minps(XMMRegister dst, XMMRegister src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
generated by cgit v1.2.3 (git 2.39.1) at 2024-06-11 14:27:16 +0000