diff options
Diffstat (limited to 'deps/v8/src/wasm/wasm-linkage.h')
| -rw-r--r-- | deps/v8/src/wasm/wasm-linkage.h | 41 |
1 files changed, 22 insertions, 19 deletions
diff --git a/deps/v8/src/wasm/wasm-linkage.h b/deps/v8/src/wasm/wasm-linkage.h index 92390cc556..6f022207bf 100644 --- a/deps/v8/src/wasm/wasm-linkage.h +++ b/deps/v8/src/wasm/wasm-linkage.h @@ -40,6 +40,7 @@ constexpr DoubleRegister kFpReturnRegisters[] = {xmm1, xmm2}; // =========================================================================== constexpr Register kGpParamRegisters[] = {r3, r0, r1, r2}; constexpr Register kGpReturnRegisters[] = {r0, r1}; +// ARM d-registers must be in ascending order for correct allocation. constexpr DoubleRegister kFpParamRegisters[] = {d0, d1, d2, d3, d4, d5, d6, d7}; constexpr DoubleRegister kFpReturnRegisters[] = {d0, d1}; @@ -129,9 +130,11 @@ class LinkageAllocator { #if V8_TARGET_ARCH_ARM switch (rep) { case MachineRepresentation::kFloat32: - return extra_float_reg >= 0 || fp_offset_ < fp_count_; + return extra_float_reg_ >= 0 || + (extra_double_reg_ >= 0 && extra_double_reg_ < 16) || + (fp_offset_ < fp_count_ && fp_regs_[fp_offset_].code() < 16); case MachineRepresentation::kFloat64: - return extra_double_reg >= 0 || fp_offset_ < fp_count_; + return extra_double_reg_ >= 0 || fp_offset_ < fp_count_; case MachineRepresentation::kSimd128: return ((fp_offset_ + 1) & ~1) + 1 < fp_count_; default: @@ -151,10 +154,10 @@ class LinkageAllocator { #if V8_TARGET_ARCH_ARM switch (rep) { case MachineRepresentation::kFloat32: { - // Use the extra S-register if we can. - if (extra_float_reg >= 0) { - int reg_code = extra_float_reg; - extra_float_reg = -1; + // Use the extra S-register if there is one. + if (extra_float_reg_ >= 0) { + int reg_code = extra_float_reg_; + extra_float_reg_ = -1; return reg_code; } // Allocate a D-register and split into 2 float registers. @@ -162,15 +165,15 @@ class LinkageAllocator { DCHECK_GT(16, d_reg_code); // D-registers 16 - 31 can't split. int reg_code = d_reg_code * 2; // Save the extra S-register. - DCHECK_EQ(-1, extra_float_reg); - extra_float_reg = reg_code + 1; + DCHECK_EQ(-1, extra_float_reg_); + extra_float_reg_ = reg_code + 1; return reg_code; } case MachineRepresentation::kFloat64: { - // Use an extra D-register if we can. - if (extra_double_reg >= 0) { - int reg_code = extra_double_reg; - extra_double_reg = -1; + // Use the extra D-register if there is one. + if (extra_double_reg_ >= 0) { + int reg_code = extra_double_reg_; + extra_double_reg_ = -1; return reg_code; } DCHECK_LT(fp_offset_, fp_count_); @@ -178,16 +181,16 @@ class LinkageAllocator { } case MachineRepresentation::kSimd128: { // Q-register must be an even-odd pair, so we must try to allocate at - // the end, not using extra_double_reg. If we are at an odd D-register, - // skip past it (saving it to extra_double_reg). + // the end, not using extra_double_reg_. If we are at an odd D-register, + // skip past it (saving it to extra_double_reg_). DCHECK_LT(((fp_offset_ + 1) & ~1) + 1, fp_count_); int d_reg1_code = fp_regs_[fp_offset_++].code(); if (d_reg1_code % 2 != 0) { - // If we're misaligned then extra_double_reg must have been consumed. - DCHECK_EQ(-1, extra_double_reg); + // If we're misaligned then extra_double_reg_ must have been consumed. + DCHECK_EQ(-1, extra_double_reg_); int odd_double_reg = d_reg1_code; d_reg1_code = fp_regs_[fp_offset_++].code(); - extra_double_reg = odd_double_reg; + extra_double_reg_ = odd_double_reg; } // Combine the current D-register with the next to form a Q-register. int d_reg2_code = fp_regs_[fp_offset_++].code(); @@ -244,8 +247,8 @@ class LinkageAllocator { // ARM FP register aliasing may require splitting or merging double registers. // Track fragments of registers below fp_offset_ here. There can only be one // extra float and double register. - int extra_float_reg = -1; - int extra_double_reg = -1; + int extra_float_reg_ = -1; + int extra_double_reg_ = -1; #endif int stack_offset_ = 0; |