diff options
Diffstat (limited to 'deps/v8/src/mips/macro-assembler-mips.h')
| -rw-r--r-- | deps/v8/src/mips/macro-assembler-mips.h | 179 |
1 files changed, 81 insertions, 98 deletions
diff --git a/deps/v8/src/mips/macro-assembler-mips.h b/deps/v8/src/mips/macro-assembler-mips.h index 37d2c59270..3278932e19 100644 --- a/deps/v8/src/mips/macro-assembler-mips.h +++ b/deps/v8/src/mips/macro-assembler-mips.h @@ -210,30 +210,30 @@ class TurboAssembler : public Assembler { #undef COND_TYPED_ARGS #undef COND_ARGS - // Wrapper functions for the different cmp/branch types. - inline void BranchF32(Label* target, Label* nan, Condition cc, - FPURegister cmp1, FPURegister cmp2, - BranchDelaySlot bd = PROTECT) { - BranchFCommon(S, target, nan, cc, cmp1, cmp2, bd); + // Floating point branches + void CompareF32(FPUCondition cc, FPURegister cmp1, FPURegister cmp2) { + CompareF(S, cc, cmp1, cmp2); } - inline void BranchF64(Label* target, Label* nan, Condition cc, - FPURegister cmp1, FPURegister cmp2, - BranchDelaySlot bd = PROTECT) { - BranchFCommon(D, target, nan, cc, cmp1, cmp2, bd); + void CompareIsNanF32(FPURegister cmp1, FPURegister cmp2) { + CompareIsNanF(S, cmp1, cmp2); } - // Alternate (inline) version for better readability with USE_DELAY_SLOT. - inline void BranchF64(BranchDelaySlot bd, Label* target, Label* nan, - Condition cc, FPURegister cmp1, FPURegister cmp2) { - BranchF64(target, nan, cc, cmp1, cmp2, bd); + void CompareF64(FPUCondition cc, FPURegister cmp1, FPURegister cmp2) { + CompareF(D, cc, cmp1, cmp2); } - inline void BranchF32(BranchDelaySlot bd, Label* target, Label* nan, - Condition cc, FPURegister cmp1, FPURegister cmp2) { - BranchF32(target, nan, cc, cmp1, cmp2, bd); + void CompareIsNanF64(FPURegister cmp1, FPURegister cmp2) { + CompareIsNanF(D, cmp1, cmp2); } + void BranchTrueShortF(Label* target); + void BranchFalseShortF(Label* target); + + void BranchTrueF(Label* target); + void BranchFalseF(Label* target); + + // MSA Branches void BranchMSA(Label* target, MSABranchDF df, MSABranchCondition cond, MSARegister wt, BranchDelaySlot bd = PROTECT); @@ -461,6 +461,12 @@ class TurboAssembler : public Assembler { DEFINE_INSTRUCTION(Slt); DEFINE_INSTRUCTION(Sltu); + DEFINE_INSTRUCTION(Sle); + DEFINE_INSTRUCTION(Sleu); + DEFINE_INSTRUCTION(Sgt); + DEFINE_INSTRUCTION(Sgtu); + DEFINE_INSTRUCTION(Sge); + DEFINE_INSTRUCTION(Sgeu); // MIPS32 R2 instruction macro. DEFINE_INSTRUCTION(Ror); @@ -561,6 +567,11 @@ class TurboAssembler : public Assembler { void Movt(Register rd, Register rs, uint16_t cc = 0); void Movf(Register rd, Register rs, uint16_t cc = 0); + void LoadZeroIfConditionNotZero(Register dest, Register condition); + void LoadZeroIfConditionZero(Register dest, Register condition); + void LoadZeroOnCondition(Register rd, Register rs, const Operand& rt, + Condition cond); + void Clz(Register rd, Register rs); void Ctz(Register rd, Register rs); void Popcnt(Register rd, Register rs); @@ -573,22 +584,25 @@ class TurboAssembler : public Assembler { Register left_high, Register right_low, Register right_high); void ShlPair(Register dst_low, Register dst_high, Register src_low, - Register src_high, Register shift); + Register src_high, Register shift, Register scratch1, + Register scratch2); void ShlPair(Register dst_low, Register dst_high, Register src_low, - Register src_high, uint32_t shift); + Register src_high, uint32_t shift, Register scratch); void ShrPair(Register dst_low, Register dst_high, Register src_low, - Register src_high, Register shift); + Register src_high, Register shift, Register scratch1, + Register scratch2); void ShrPair(Register dst_low, Register dst_high, Register src_low, - Register src_high, uint32_t shift); + Register src_high, uint32_t shift, Register scratch); void SarPair(Register dst_low, Register dst_high, Register src_low, - Register src_high, Register shift); + Register src_high, Register shift, Register scratch1, + Register scratch2); void SarPair(Register dst_low, Register dst_high, Register src_low, - Register src_high, uint32_t shift); + Register src_high, uint32_t shift, Register scratch); // MIPS32 R2 instruction macro. void Ins(Register rt, Register rs, uint16_t pos, uint16_t size); @@ -615,6 +629,18 @@ class TurboAssembler : public Assembler { void Floor_w_d(FPURegister fd, FPURegister fs); void Ceil_w_d(FPURegister fd, FPURegister fs); + // Round double functions + void Trunc_d_d(FPURegister fd, FPURegister fs); + void Round_d_d(FPURegister fd, FPURegister fs); + void Floor_d_d(FPURegister fd, FPURegister fs); + void Ceil_d_d(FPURegister fd, FPURegister fs); + + // Round float functions + void Trunc_s_s(FPURegister fd, FPURegister fs); + void Round_s_s(FPURegister fd, FPURegister fs); + void Floor_s_s(FPURegister fd, FPURegister fs); + void Ceil_s_s(FPURegister fd, FPURegister fs); + // FP32 mode: Move the general purpose register into // the high part of the double-register pair. // FP64 mode: Move the general-purpose register into @@ -742,63 +768,19 @@ class TurboAssembler : public Assembler { void Move(FPURegister dst, uint64_t src); // ------------------------------------------------------------------------- - // Overflow handling functions. - // Usage: first call the appropriate arithmetic function, then call one of the - // jump functions with the overflow_dst register as the second parameter. - - inline void AddBranchOvf(Register dst, Register left, const Operand& right, - Label* overflow_label, Register scratch = at) { - AddBranchOvf(dst, left, right, overflow_label, nullptr, scratch); - } - - inline void AddBranchNoOvf(Register dst, Register left, const Operand& right, - Label* no_overflow_label, Register scratch = at) { - AddBranchOvf(dst, left, right, nullptr, no_overflow_label, scratch); - } - - void AddBranchOvf(Register dst, Register left, const Operand& right, - Label* overflow_label, Label* no_overflow_label, - Register scratch = at); - - void AddBranchOvf(Register dst, Register left, Register right, - Label* overflow_label, Label* no_overflow_label, - Register scratch = at); - - inline void SubBranchOvf(Register dst, Register left, const Operand& right, - Label* overflow_label, Register scratch = at) { - SubBranchOvf(dst, left, right, overflow_label, nullptr, scratch); - } - - inline void SubBranchNoOvf(Register dst, Register left, const Operand& right, - Label* no_overflow_label, Register scratch = at) { - SubBranchOvf(dst, left, right, nullptr, no_overflow_label, scratch); - } - - void SubBranchOvf(Register dst, Register left, const Operand& right, - Label* overflow_label, Label* no_overflow_label, - Register scratch = at); - - void SubBranchOvf(Register dst, Register left, Register right, - Label* overflow_label, Label* no_overflow_label, - Register scratch = at); - - inline void MulBranchOvf(Register dst, Register left, const Operand& right, - Label* overflow_label, Register scratch = at) { - MulBranchOvf(dst, left, right, overflow_label, nullptr, scratch); - } - - inline void MulBranchNoOvf(Register dst, Register left, const Operand& right, - Label* no_overflow_label, Register scratch = at) { - MulBranchOvf(dst, left, right, nullptr, no_overflow_label, scratch); - } - - void MulBranchOvf(Register dst, Register left, const Operand& right, - Label* overflow_label, Label* no_overflow_label, - Register scratch = at); - - void MulBranchOvf(Register dst, Register left, Register right, - Label* overflow_label, Label* no_overflow_label, - Register scratch = at); + // Overflow operations. + + // AddOverflow sets overflow register to a negative value if + // overflow occured, otherwise it is zero or positive + void AddOverflow(Register dst, Register left, const Operand& right, + Register overflow); + // SubOverflow sets overflow register to a negative value if + // overflow occured, otherwise it is zero or positive + void SubOverflow(Register dst, Register left, const Operand& right, + Register overflow); + // MulOverflow sets overflow register to zero if no overflow occured + void MulOverflow(Register dst, Register left, const Operand& right, + Register overflow); // Number of instructions needed for calculation of switch table entry address #ifdef _MIPS_ARCH_MIPS32R6 @@ -840,17 +822,6 @@ class TurboAssembler : public Assembler { // Get the actual activation frame alignment for target environment. static int ActivationFrameAlignment(); - // Alias functions for backward compatibility. - inline void BranchF(Label* target, Label* nan, Condition cc, FPURegister cmp1, - FPURegister cmp2, BranchDelaySlot bd = PROTECT) { - BranchF64(target, nan, cc, cmp1, cmp2, bd); - } - - inline void BranchF(BranchDelaySlot bd, Label* target, Label* nan, - Condition cc, FPURegister cmp1, FPURegister cmp2) { - BranchF64(bd, target, nan, cc, cmp1, cmp2); - } - // Compute the start of the generated instruction stream from the current PC. // This is an alternative to embedding the {CodeObject} handle as a reference. void ComputeCodeStartAddress(Register dst); @@ -874,14 +845,11 @@ class TurboAssembler : public Assembler { void CallCFunctionHelper(Register function_base, int16_t function_offset, int num_reg_arguments, int num_double_arguments); - // Common implementation of BranchF functions for the different formats. - void BranchFCommon(SecondaryField sizeField, Label* target, Label* nan, - Condition cc, FPURegister cmp1, FPURegister cmp2, - BranchDelaySlot bd = PROTECT); + void CompareF(SecondaryField sizeField, FPUCondition cc, FPURegister cmp1, + FPURegister cmp2); - void BranchShortF(SecondaryField sizeField, Label* target, Condition cc, - FPURegister cmp1, FPURegister cmp2, - BranchDelaySlot bd = PROTECT); + void CompareIsNanF(SecondaryField sizeField, FPURegister cmp1, + FPURegister cmp2); void BranchShortMSA(MSABranchDF df, Label* target, MSABranchCondition cond, MSARegister wt, BranchDelaySlot bd = PROTECT); @@ -914,6 +882,14 @@ class TurboAssembler : public Assembler { BranchDelaySlot bdslot); void BranchAndLinkLong(Label* L, BranchDelaySlot bdslot); + template <typename RoundFunc> + void RoundDouble(FPURegister dst, FPURegister src, FPURoundingMode mode, + RoundFunc round); + + template <typename RoundFunc> + void RoundFloat(FPURegister dst, FPURegister src, FPURoundingMode mode, + RoundFunc round); + // Push a fixed frame, consisting of ra, fp. void PushCommonFrame(Register marker_reg = no_reg); }; @@ -1099,7 +1075,11 @@ const Operand& rt = Operand(zero_reg), BranchDelaySlot bd = PROTECT bool builtin_exit_frame = false); // Generates a trampoline to jump to the off-heap instruction stream. - void JumpToInstructionStream(const InstructionStream* stream); + void JumpToInstructionStream(Address entry); + + // --------------------------------------------------------------------------- + // In-place weak references. + void LoadWeakValue(Register out, Register in, Label* target_if_cleared); // ------------------------------------------------------------------------- // StatsCounter support. @@ -1143,6 +1123,9 @@ const Operand& rt = Operand(zero_reg), BranchDelaySlot bd = PROTECT // Abort execution if argument is not a FixedArray, enabled via --debug-code. void AssertFixedArray(Register object); + // Abort execution if argument is not a Constructor, enabled via --debug-code. + void AssertConstructor(Register object); + // Abort execution if argument is not a JSFunction, enabled via --debug-code. void AssertFunction(Register object); |