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Diffstat (limited to 'deps/v8/src/mips/assembler-mips.cc')
-rw-r--r--deps/v8/src/mips/assembler-mips.cc130
1 files changed, 76 insertions, 54 deletions
diff --git a/deps/v8/src/mips/assembler-mips.cc b/deps/v8/src/mips/assembler-mips.cc
index 3860fe4e19..a8b6cc7c32 100644
--- a/deps/v8/src/mips/assembler-mips.cc
+++ b/deps/v8/src/mips/assembler-mips.cc
@@ -296,6 +296,7 @@ void Assembler::GetCode(CodeDesc* desc) {
desc->instr_size = pc_offset();
desc->reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos();
desc->origin = this;
+ desc->constant_pool_size = 0;
}
@@ -1335,17 +1336,23 @@ void Assembler::bne(Register rs, Register rt, int16_t offset) {
void Assembler::bovc(Register rs, Register rt, int16_t offset) {
DCHECK(IsMipsArchVariant(kMips32r6));
- DCHECK(!(rs.is(zero_reg)));
- DCHECK(rs.code() >= rt.code());
- GenInstrImmediate(ADDI, rs, rt, offset, CompactBranchType::COMPACT_BRANCH);
+ DCHECK(!rs.is(zero_reg));
+ if (rs.code() >= rt.code()) {
+ GenInstrImmediate(ADDI, rs, rt, offset, CompactBranchType::COMPACT_BRANCH);
+ } else {
+ GenInstrImmediate(ADDI, rt, rs, offset, CompactBranchType::COMPACT_BRANCH);
+ }
}
void Assembler::bnvc(Register rs, Register rt, int16_t offset) {
DCHECK(IsMipsArchVariant(kMips32r6));
- DCHECK(!(rs.is(zero_reg)));
- DCHECK(rs.code() >= rt.code());
- GenInstrImmediate(DADDI, rs, rt, offset, CompactBranchType::COMPACT_BRANCH);
+ DCHECK(!rs.is(zero_reg));
+ if (rs.code() >= rt.code()) {
+ GenInstrImmediate(DADDI, rs, rt, offset, CompactBranchType::COMPACT_BRANCH);
+ } else {
+ GenInstrImmediate(DADDI, rt, rs, offset, CompactBranchType::COMPACT_BRANCH);
+ }
}
@@ -1652,7 +1659,7 @@ void Assembler::sll(Register rd,
// nop(int/NopMarkerTypes) or MarkCode(int/NopMarkerTypes) pseudo
// instructions.
DCHECK(coming_from_nop || !(rd.is(zero_reg) && rt.is(zero_reg)));
- GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, SLL);
+ GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, SLL);
}
@@ -1662,7 +1669,7 @@ void Assembler::sllv(Register rd, Register rt, Register rs) {
void Assembler::srl(Register rd, Register rt, uint16_t sa) {
- GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, SRL);
+ GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, SRL);
}
@@ -1672,7 +1679,7 @@ void Assembler::srlv(Register rd, Register rt, Register rs) {
void Assembler::sra(Register rd, Register rt, uint16_t sa) {
- GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, SRA);
+ GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, SRA);
}
@@ -1693,7 +1700,7 @@ void Assembler::rotr(Register rd, Register rt, uint16_t sa) {
void Assembler::rotrv(Register rd, Register rt, Register rs) {
// Should be called via MacroAssembler::Ror.
- DCHECK(rd.is_valid() && rt.is_valid() && rs.is_valid() );
+ DCHECK(rd.is_valid() && rt.is_valid() && rs.is_valid());
DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
Instr instr = SPECIAL | (rs.code() << kRsShift) | (rt.code() << kRtShift)
| (rd.code() << kRdShift) | (1 << kSaShift) | SRLV;
@@ -1701,6 +1708,16 @@ void Assembler::rotrv(Register rd, Register rt, Register rs) {
}
+void Assembler::lsa(Register rd, Register rt, Register rs, uint8_t sa) {
+ DCHECK(rd.is_valid() && rt.is_valid() && rs.is_valid());
+ DCHECK(sa < 5 && sa > 0);
+ DCHECK(IsMipsArchVariant(kMips32r6));
+ Instr instr = SPECIAL | (rs.code() << kRsShift) | (rt.code() << kRtShift) |
+ (rd.code() << kRdShift) | (sa - 1) << kSaShift | LSA;
+ emit(instr);
+}
+
+
// ------------Memory-instructions-------------
// Helper for base-reg + offset, when offset is larger than int16.
@@ -1818,7 +1835,7 @@ void Assembler::lui(Register rd, int32_t j) {
}
-void Assembler::aui(Register rs, Register rt, int32_t j) {
+void Assembler::aui(Register rt, Register rs, int32_t j) {
// This instruction uses same opcode as 'lui'. The difference in encoding is
// 'lui' has zero reg. for rs field.
DCHECK(!(rs.is(zero_reg)));
@@ -2194,13 +2211,13 @@ void Assembler::DoubleAsTwoUInt32(double d, uint32_t* lo, uint32_t* hi) {
void Assembler::movn_s(FPURegister fd, FPURegister fs, Register rt) {
- DCHECK(IsMipsArchVariant(kMips32r2));
+ DCHECK(!IsMipsArchVariant(kMips32r6));
GenInstrRegister(COP1, S, rt, fs, fd, MOVN_C);
}
void Assembler::movn_d(FPURegister fd, FPURegister fs, Register rt) {
- DCHECK(IsMipsArchVariant(kMips32r2));
+ DCHECK(!IsMipsArchVariant(kMips32r6));
GenInstrRegister(COP1, D, rt, fs, fd, MOVN_C);
}
@@ -2267,19 +2284,19 @@ void Assembler::selnez_s(FPURegister fd, FPURegister fs, FPURegister ft) {
void Assembler::movz_s(FPURegister fd, FPURegister fs, Register rt) {
- DCHECK(IsMipsArchVariant(kMips32r2));
+ DCHECK(!IsMipsArchVariant(kMips32r6));
GenInstrRegister(COP1, S, rt, fs, fd, MOVZ_C);
}
void Assembler::movz_d(FPURegister fd, FPURegister fs, Register rt) {
- DCHECK(IsMipsArchVariant(kMips32r2));
+ DCHECK(!IsMipsArchVariant(kMips32r6));
GenInstrRegister(COP1, D, rt, fs, fd, MOVZ_C);
}
void Assembler::movt_s(FPURegister fd, FPURegister fs, uint16_t cc) {
- DCHECK(IsMipsArchVariant(kMips32r2));
+ DCHECK(!IsMipsArchVariant(kMips32r6));
FPURegister ft;
ft.reg_code = (cc & 0x0007) << 2 | 1;
GenInstrRegister(COP1, S, ft, fs, fd, MOVF);
@@ -2287,7 +2304,7 @@ void Assembler::movt_s(FPURegister fd, FPURegister fs, uint16_t cc) {
void Assembler::movt_d(FPURegister fd, FPURegister fs, uint16_t cc) {
- DCHECK(IsMipsArchVariant(kMips32r2));
+ DCHECK(!IsMipsArchVariant(kMips32r6));
FPURegister ft;
ft.reg_code = (cc & 0x0007) << 2 | 1;
GenInstrRegister(COP1, D, ft, fs, fd, MOVF);
@@ -2295,7 +2312,7 @@ void Assembler::movt_d(FPURegister fd, FPURegister fs, uint16_t cc) {
void Assembler::movf_s(FPURegister fd, FPURegister fs, uint16_t cc) {
- DCHECK(IsMipsArchVariant(kMips32r2));
+ DCHECK(!IsMipsArchVariant(kMips32r6));
FPURegister ft;
ft.reg_code = (cc & 0x0007) << 2 | 0;
GenInstrRegister(COP1, S, ft, fs, fd, MOVF);
@@ -2303,7 +2320,7 @@ void Assembler::movf_s(FPURegister fd, FPURegister fs, uint16_t cc) {
void Assembler::movf_d(FPURegister fd, FPURegister fs, uint16_t cc) {
- DCHECK(IsMipsArchVariant(kMips32r2));
+ DCHECK(!IsMipsArchVariant(kMips32r6));
FPURegister ft;
ft.reg_code = (cc & 0x0007) << 2 | 0;
GenInstrRegister(COP1, D, ft, fs, fd, MOVF);
@@ -2489,55 +2506,71 @@ void Assembler::rint_d(FPURegister fd, FPURegister fs) { rint(D, fd, fs); }
void Assembler::cvt_l_s(FPURegister fd, FPURegister fs) {
- DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
+ DCHECK((IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) &&
+ IsFp64Mode());
GenInstrRegister(COP1, S, f0, fs, fd, CVT_L_S);
}
void Assembler::cvt_l_d(FPURegister fd, FPURegister fs) {
- DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
+ DCHECK((IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) &&
+ IsFp64Mode());
GenInstrRegister(COP1, D, f0, fs, fd, CVT_L_D);
}
void Assembler::trunc_l_s(FPURegister fd, FPURegister fs) {
- DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
+ DCHECK((IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) &&
+ IsFp64Mode());
GenInstrRegister(COP1, S, f0, fs, fd, TRUNC_L_S);
}
void Assembler::trunc_l_d(FPURegister fd, FPURegister fs) {
- DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
+ DCHECK((IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) &&
+ IsFp64Mode());
GenInstrRegister(COP1, D, f0, fs, fd, TRUNC_L_D);
}
void Assembler::round_l_s(FPURegister fd, FPURegister fs) {
+ DCHECK((IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) &&
+ IsFp64Mode());
GenInstrRegister(COP1, S, f0, fs, fd, ROUND_L_S);
}
void Assembler::round_l_d(FPURegister fd, FPURegister fs) {
+ DCHECK((IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) &&
+ IsFp64Mode());
GenInstrRegister(COP1, D, f0, fs, fd, ROUND_L_D);
}
void Assembler::floor_l_s(FPURegister fd, FPURegister fs) {
+ DCHECK((IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) &&
+ IsFp64Mode());
GenInstrRegister(COP1, S, f0, fs, fd, FLOOR_L_S);
}
void Assembler::floor_l_d(FPURegister fd, FPURegister fs) {
+ DCHECK((IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) &&
+ IsFp64Mode());
GenInstrRegister(COP1, D, f0, fs, fd, FLOOR_L_D);
}
void Assembler::ceil_l_s(FPURegister fd, FPURegister fs) {
+ DCHECK((IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) &&
+ IsFp64Mode());
GenInstrRegister(COP1, S, f0, fs, fd, CEIL_L_S);
}
void Assembler::ceil_l_d(FPURegister fd, FPURegister fs) {
+ DCHECK((IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) &&
+ IsFp64Mode());
GenInstrRegister(COP1, D, f0, fs, fd, CEIL_L_D);
}
@@ -2632,7 +2665,8 @@ void Assembler::cvt_s_w(FPURegister fd, FPURegister fs) {
void Assembler::cvt_s_l(FPURegister fd, FPURegister fs) {
- DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
+ DCHECK((IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) &&
+ IsFp64Mode());
GenInstrRegister(COP1, L, f0, fs, fd, CVT_S_L);
}
@@ -2648,7 +2682,8 @@ void Assembler::cvt_d_w(FPURegister fd, FPURegister fs) {
void Assembler::cvt_d_l(FPURegister fd, FPURegister fs) {
- DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
+ DCHECK((IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) &&
+ IsFp64Mode());
GenInstrRegister(COP1, L, f0, fs, fd, CVT_D_L);
}
@@ -2796,6 +2831,7 @@ void Assembler::GrowBuffer() {
// Set up new buffer.
desc.buffer = NewArray<byte>(desc.buffer_size);
+ desc.origin = this;
desc.instr_size = pc_offset();
desc.reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos();
@@ -2829,54 +2865,42 @@ void Assembler::GrowBuffer() {
void Assembler::db(uint8_t data) {
- CheckBuffer();
- *reinterpret_cast<uint8_t*>(pc_) = data;
- pc_ += sizeof(uint8_t);
+ CheckForEmitInForbiddenSlot();
+ EmitHelper(data);
}
void Assembler::dd(uint32_t data) {
- CheckBuffer();
- *reinterpret_cast<uint32_t*>(pc_) = data;
- pc_ += sizeof(uint32_t);
+ CheckForEmitInForbiddenSlot();
+ EmitHelper(data);
}
void Assembler::dq(uint64_t data) {
- CheckBuffer();
- *reinterpret_cast<uint64_t*>(pc_) = data;
- pc_ += sizeof(uint64_t);
+ CheckForEmitInForbiddenSlot();
+ EmitHelper(data);
}
void Assembler::dd(Label* label) {
- CheckBuffer();
- RecordRelocInfo(RelocInfo::INTERNAL_REFERENCE);
uint32_t data;
+ CheckForEmitInForbiddenSlot();
if (label->is_bound()) {
data = reinterpret_cast<uint32_t>(buffer_ + label->pos());
} else {
data = jump_address(label);
internal_reference_positions_.insert(label->pos());
}
- *reinterpret_cast<uint32_t*>(pc_) = data;
- pc_ += sizeof(uint32_t);
-}
-
-
-void Assembler::emit_code_stub_address(Code* stub) {
- CheckBuffer();
- *reinterpret_cast<uint32_t*>(pc_) =
- reinterpret_cast<uint32_t>(stub->instruction_start());
- pc_ += sizeof(uint32_t);
+ RecordRelocInfo(RelocInfo::INTERNAL_REFERENCE);
+ EmitHelper(data);
}
void Assembler::RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data) {
// We do not try to reuse pool constants.
- RelocInfo rinfo(pc_, rmode, data, NULL);
+ RelocInfo rinfo(isolate(), pc_, rmode, data, NULL);
if (rmode >= RelocInfo::COMMENT &&
- rmode <= RelocInfo::DEBUG_BREAK_SLOT_AT_CONSTRUCT_CALL) {
+ rmode <= RelocInfo::DEBUG_BREAK_SLOT_AT_CALL) {
// Adjust code for new modes.
DCHECK(RelocInfo::IsDebugBreakSlot(rmode)
|| RelocInfo::IsComment(rmode)
@@ -2891,10 +2915,8 @@ void Assembler::RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data) {
}
DCHECK(buffer_space() >= kMaxRelocSize); // Too late to grow buffer here.
if (rmode == RelocInfo::CODE_TARGET_WITH_ID) {
- RelocInfo reloc_info_with_ast_id(pc_,
- rmode,
- RecordedAstId().ToInt(),
- NULL);
+ RelocInfo reloc_info_with_ast_id(isolate(), pc_, rmode,
+ RecordedAstId().ToInt(), NULL);
ClearRecordedAstId();
reloc_info_writer.Write(&reloc_info_with_ast_id);
} else {
@@ -3006,7 +3028,7 @@ void Assembler::QuietNaN(HeapObject* object) {
// There is an optimization below, which emits a nop when the address
// fits in just 16 bits. This is unlikely to help, and should be benchmarked,
// and possibly removed.
-void Assembler::set_target_address_at(Address pc,
+void Assembler::set_target_address_at(Isolate* isolate, Address pc,
Address target,
ICacheFlushMode icache_flush_mode) {
Instr instr2 = instr_at(pc + kInstrSize);
@@ -3028,7 +3050,7 @@ void Assembler::set_target_address_at(Address pc,
if (icache_flush_mode != SKIP_ICACHE_FLUSH) {
- CpuFeatures::FlushICache(pc, 2 * sizeof(int32_t));
+ Assembler::FlushICache(isolate, pc, 2 * sizeof(int32_t));
}
}
generated by cgit v1.2.3 (git 2.39.1) at 2024-06-02 19:33:58 +0000