summaryrefslogtreecommitdiff
path: root/deps/v8/src/compiler/register-allocator.h
diff options
context:
space:
mode:
Diffstat (limited to 'deps/v8/src/compiler/register-allocator.h')
-rw-r--r--deps/v8/src/compiler/register-allocator.h107
1 files changed, 75 insertions, 32 deletions
diff --git a/deps/v8/src/compiler/register-allocator.h b/deps/v8/src/compiler/register-allocator.h
index 443232abb1..b96a43ccec 100644
--- a/deps/v8/src/compiler/register-allocator.h
+++ b/deps/v8/src/compiler/register-allocator.h
@@ -135,6 +135,8 @@ class LifetimePosition final {
return this->value_ >= that.value_;
}
+ void Print() const;
+
static inline LifetimePosition Invalid() { return LifetimePosition(); }
static inline LifetimePosition MaxPosition() {
@@ -194,6 +196,24 @@ class UseInterval final : public ZoneObject {
return start_ <= point && point < end_;
}
+ // Returns the index of the first gap covered by this interval.
+ int FirstGapIndex() const {
+ int ret = start_.ToInstructionIndex();
+ if (start_.IsInstructionPosition()) {
+ ++ret;
+ }
+ return ret;
+ }
+
+ // Returns the index of the last gap covered by this interval.
+ int LastGapIndex() const {
+ int ret = end_.ToInstructionIndex();
+ if (end_.IsGapPosition() && end_.IsStart()) {
+ --ret;
+ }
+ return ret;
+ }
+
private:
LifetimePosition start_;
LifetimePosition end_;
@@ -299,7 +319,9 @@ class LiveRange : public ZoneObject {
InstructionOperand GetAssignedOperand() const;
- MachineType machine_type() const { return MachineTypeField::decode(bits_); }
+ MachineRepresentation representation() const {
+ return RepresentationField::decode(bits_);
+ }
int assigned_register() const { return AssignedRegisterField::decode(bits_); }
bool HasRegisterAssigned() const {
@@ -378,7 +400,10 @@ class LiveRange : public ZoneObject {
bool Covers(LifetimePosition position) const;
LifetimePosition FirstIntersection(LiveRange* other) const;
- void Verify() const;
+ void VerifyChildStructure() const {
+ VerifyIntervals();
+ VerifyPositions();
+ }
void ConvertUsesToOperand(const InstructionOperand& op,
const InstructionOperand& spill_op);
@@ -391,6 +416,8 @@ class LiveRange : public ZoneObject {
void set_weight(float weight) { weight_ = weight; }
LiveRangeGroup* group() const { return group_; }
void set_group(LiveRangeGroup* group) { group_ = group; }
+ void Print(const RegisterConfiguration* config, bool with_children) const;
+ void Print(bool with_children) const;
static const int kInvalidSize = -1;
static const float kInvalidWeight;
@@ -398,10 +425,9 @@ class LiveRange : public ZoneObject {
private:
friend class TopLevelLiveRange;
- explicit LiveRange(int relative_id, MachineType machine_type,
+ explicit LiveRange(int relative_id, MachineRepresentation rep,
TopLevelLiveRange* top_level);
- void AppendAsChild(TopLevelLiveRange* other);
void UpdateParentForAllChildren(TopLevelLiveRange* new_top_level);
void set_spilled(bool value) { bits_ = SpilledField::update(bits_, value); }
@@ -410,9 +436,12 @@ class LiveRange : public ZoneObject {
void AdvanceLastProcessedMarker(UseInterval* to_start_of,
LifetimePosition but_not_past) const;
+ void VerifyPositions() const;
+ void VerifyIntervals() const;
+
typedef BitField<bool, 0, 1> SpilledField;
typedef BitField<int32_t, 6, 6> AssignedRegisterField;
- typedef BitField<MachineType, 12, 15> MachineTypeField;
+ typedef BitField<MachineRepresentation, 12, 8> RepresentationField;
// Unique among children and splinters of the same virtual register.
int relative_id_;
@@ -465,7 +494,7 @@ class LiveRangeGroup final : public ZoneObject {
class TopLevelLiveRange final : public LiveRange {
public:
- explicit TopLevelLiveRange(int vreg, MachineType machine_type);
+ explicit TopLevelLiveRange(int vreg, MachineRepresentation rep);
int spill_start_index() const { return spill_start_index_; }
bool IsFixed() const { return vreg_ < 0; }
@@ -532,16 +561,16 @@ class TopLevelLiveRange final : public LiveRange {
AllocatedOperand GetSpillRangeOperand() const;
- void SpillAtDefinition(Zone* zone, int gap_index,
- InstructionOperand* operand);
+ void RecordSpillLocation(Zone* zone, int gap_index,
+ InstructionOperand* operand);
void SetSpillOperand(InstructionOperand* operand);
void SetSpillStartIndex(int start) {
spill_start_index_ = Min(start, spill_start_index_);
}
- void CommitSpillsAtDefinition(InstructionSequence* sequence,
- const InstructionOperand& operand,
- bool might_be_duplicated);
+ void CommitSpillMoves(InstructionSequence* sequence,
+ const InstructionOperand& operand,
+ bool might_be_duplicated);
// If all the children of this range are spilled in deferred blocks, and if
// for any non-spilled child with a use position requiring a slot, that range
@@ -550,7 +579,12 @@ class TopLevelLiveRange final : public LiveRange {
// and instead let the LiveRangeConnector perform the spills within the
// deferred blocks. If so, we insert here spills for non-spilled ranges
// with slot use positions.
- void MarkSpilledInDeferredBlock(const InstructionSequence* code);
+ void MarkSpilledInDeferredBlock() {
+ spill_start_index_ = -1;
+ spilled_in_deferred_blocks_ = true;
+ spill_move_insertion_locations_ = nullptr;
+ }
+
bool TryCommitSpillInDeferredBlock(InstructionSequence* code,
const InstructionOperand& spill_operand);
@@ -567,22 +601,25 @@ class TopLevelLiveRange final : public LiveRange {
int debug_virt_reg() const;
#endif
+ void Verify() const;
+ void VerifyChildrenInOrder() const;
+
int GetNextChildId() {
return IsSplinter() ? splintered_from()->GetNextChildId()
: ++last_child_id_;
}
+ int GetChildCount() const { return last_child_id_ + 1; }
+
bool IsSpilledOnlyInDeferredBlocks() const {
return spilled_in_deferred_blocks_;
}
- struct SpillAtDefinitionList;
+ struct SpillMoveInsertionList;
- SpillAtDefinitionList* spills_at_definition() const {
- return spills_at_definition_;
+ SpillMoveInsertionList* spill_move_insertion_locations() const {
+ return spill_move_insertion_locations_;
}
- void set_last_child(LiveRange* range) { last_child_ = range; }
- LiveRange* last_child() const { return last_child_; }
TopLevelLiveRange* splinter() const { return splinter_; }
void SetSplinter(TopLevelLiveRange* splinter) {
DCHECK_NULL(splinter_);
@@ -594,6 +631,9 @@ class TopLevelLiveRange final : public LiveRange {
splinter->SetSplinteredFrom(this);
}
+ void MarkHasPreassignedSlot() { has_preassigned_slot_ = true; }
+ bool has_preassigned_slot() const { return has_preassigned_slot_; }
+
private:
void SetSplinteredFrom(TopLevelLiveRange* splinter_parent);
@@ -610,14 +650,14 @@ class TopLevelLiveRange final : public LiveRange {
InstructionOperand* spill_operand_;
SpillRange* spill_range_;
};
- SpillAtDefinitionList* spills_at_definition_;
+ SpillMoveInsertionList* spill_move_insertion_locations_;
// TODO(mtrofin): generalize spilling after definition, currently specialized
// just for spill in a single deferred block.
bool spilled_in_deferred_blocks_;
int spill_start_index_;
- LiveRange* last_child_;
UsePosition* last_pos_;
TopLevelLiveRange* splinter_;
+ bool has_preassigned_slot_;
DISALLOW_COPY_AND_ASSIGN(TopLevelLiveRange);
};
@@ -643,6 +683,7 @@ class SpillRange final : public ZoneObject {
int ByteWidth() const;
bool IsEmpty() const { return live_ranges_.empty(); }
bool TryMerge(SpillRange* other);
+ bool HasSlot() const { return assigned_slot_ != kUnassignedSlot; }
void set_assigned_slot(int index) {
DCHECK_EQ(kUnassignedSlot, assigned_slot_);
@@ -658,6 +699,7 @@ class SpillRange final : public ZoneObject {
ZoneVector<TopLevelLiveRange*>& live_ranges() { return live_ranges_; }
int byte_width() const { return byte_width_; }
RegisterKind kind() const { return kind_; }
+ void Print() const;
private:
LifetimePosition End() const { return end_position_; }
@@ -709,6 +751,8 @@ class RegisterAllocationData final : public ZoneObject {
InstructionOperand* operand;
};
typedef ZoneVector<DelayedReference> DelayedReferences;
+ typedef ZoneVector<std::pair<TopLevelLiveRange*, int>>
+ RangesWithPreassignedSlots;
RegisterAllocationData(const RegisterConfiguration* config,
Zone* allocation_zone, Frame* frame,
@@ -746,12 +790,12 @@ class RegisterAllocationData final : public ZoneObject {
const char* debug_name() const { return debug_name_; }
const RegisterConfiguration* config() const { return config_; }
- MachineType MachineTypeFor(int virtual_register);
+ MachineRepresentation RepresentationFor(int virtual_register);
TopLevelLiveRange* GetOrCreateLiveRangeFor(int index);
// Creates a new live range.
- TopLevelLiveRange* NewLiveRange(int index, MachineType machine_type);
- TopLevelLiveRange* NextLiveRange(MachineType machine_type);
+ TopLevelLiveRange* NewLiveRange(int index, MachineRepresentation rep);
+ TopLevelLiveRange* NextLiveRange(MachineRepresentation rep);
SpillRange* AssignSpillRangeToLiveRange(TopLevelLiveRange* range);
SpillRange* CreateSpillRangeForLiveRange(TopLevelLiveRange* range);
@@ -765,6 +809,7 @@ class RegisterAllocationData final : public ZoneObject {
}
bool ExistsUseWithoutDefinition();
+ bool RangesDefinedInDeferredStayInDeferred();
void MarkAllocated(RegisterKind kind, int index);
@@ -774,12 +819,9 @@ class RegisterAllocationData final : public ZoneObject {
PhiMapValue* GetPhiMapValueFor(int virtual_register);
bool IsBlockBoundary(LifetimePosition pos) const;
- void Print(const InstructionSequence* instructionSequence);
- void Print(const Instruction* instruction);
- void Print(const LiveRange* range, bool with_children = false);
- void Print(const InstructionOperand& op);
- void Print(const MoveOperands* move);
- void Print(const SpillRange* spill_range);
+ RangesWithPreassignedSlots& preassigned_slot_ranges() {
+ return preassigned_slot_ranges_;
+ }
private:
int GetNextLiveRangeId();
@@ -802,6 +844,7 @@ class RegisterAllocationData final : public ZoneObject {
BitVector* assigned_registers_;
BitVector* assigned_double_registers_;
int virtual_register_count_;
+ RangesWithPreassignedSlots preassigned_slot_ranges_;
DISALLOW_COPY_AND_ASSIGN(RegisterAllocationData);
};
@@ -1109,10 +1152,10 @@ class LiveRangeConnector final : public ZoneObject {
bool CanEagerlyResolveControlFlow(const InstructionBlock* block) const;
- void ResolveControlFlow(const InstructionBlock* block,
- const InstructionOperand& cur_op,
- const InstructionBlock* pred,
- const InstructionOperand& pred_op);
+ int ResolveControlFlow(const InstructionBlock* block,
+ const InstructionOperand& cur_op,
+ const InstructionBlock* pred,
+ const InstructionOperand& pred_op);
RegisterAllocationData* const data_;