diff options
Diffstat (limited to 'deps/v8/src/compiler/backend/arm')
4 files changed, 102 insertions, 39 deletions
diff --git a/deps/v8/src/compiler/backend/arm/code-generator-arm.cc b/deps/v8/src/compiler/backend/arm/code-generator-arm.cc index 88a9c52a33..65a569d755 100644 --- a/deps/v8/src/compiler/backend/arm/code-generator-arm.cc +++ b/deps/v8/src/compiler/backend/arm/code-generator-arm.cc @@ -909,10 +909,9 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( DCHECK_EQ(LeaveCC, i.OutputSBit()); break; case kArchDeoptimize: { - int deopt_state_id = + DeoptimizationExit* exit = BuildTranslation(instr, -1, 0, OutputFrameStateCombine::Ignore()); - CodeGenResult result = - AssembleDeoptimizerCall(deopt_state_id, current_source_position_); + CodeGenResult result = AssembleDeoptimizerCall(exit); if (result != kSuccess) return result; unwinding_info_writer_.MarkBlockWillExit(); break; @@ -921,10 +920,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( AssembleReturn(instr->InputAt(0)); DCHECK_EQ(LeaveCC, i.OutputSBit()); break; - case kArchStackPointer: - __ mov(i.OutputRegister(), sp); - DCHECK_EQ(LeaveCC, i.OutputSBit()); - break; case kArchFramePointer: __ mov(i.OutputRegister(), fp); DCHECK_EQ(LeaveCC, i.OutputSBit()); @@ -936,6 +931,12 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( __ mov(i.OutputRegister(), fp); } break; + case kArchStackPointerGreaterThan: { + constexpr size_t kValueIndex = 0; + DCHECK(instr->InputAt(kValueIndex)->IsRegister()); + __ cmp(sp, i.InputRegister(kValueIndex)); + break; + } case kArchTruncateDoubleToI: __ TruncateDoubleToI(isolate(), zone(), i.OutputRegister(), i.InputDoubleRegister(0), DetermineStubCallMode()); @@ -1838,6 +1839,21 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( i.InputSimd128Register(1)); break; } + case kArmF32x4Div: { + QwNeonRegister dst = i.OutputSimd128Register(); + QwNeonRegister src1 = i.InputSimd128Register(0); + QwNeonRegister src2 = i.InputSimd128Register(1); + DCHECK_EQ(dst, q0); + DCHECK_EQ(src1, q0); + DCHECK_EQ(src2, q1); +#define S_FROM_Q(reg, lane) SwVfpRegister::from_code(reg.code() * 4 + lane) + __ vdiv(S_FROM_Q(dst, 0), S_FROM_Q(src1, 0), S_FROM_Q(src2, 0)); + __ vdiv(S_FROM_Q(dst, 1), S_FROM_Q(src1, 1), S_FROM_Q(src2, 1)); + __ vdiv(S_FROM_Q(dst, 2), S_FROM_Q(src1, 2), S_FROM_Q(src2, 2)); + __ vdiv(S_FROM_Q(dst, 3), S_FROM_Q(src1, 3), S_FROM_Q(src2, 3)); +#undef S_FROM_Q + break; + } case kArmF32x4Min: { __ vmin(i.OutputSimd128Register(), i.InputSimd128Register(0), i.InputSimd128Register(1)); @@ -1902,13 +1918,18 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( break; } case kArmI32x4Shl: { + QwNeonRegister tmp = i.TempSimd128Register(0); + __ vdup(Neon32, tmp, i.InputRegister(1)); __ vshl(NeonS32, i.OutputSimd128Register(), i.InputSimd128Register(0), - i.InputInt5(1)); + tmp); break; } case kArmI32x4ShrS: { - __ vshr(NeonS32, i.OutputSimd128Register(), i.InputSimd128Register(0), - i.InputInt5(1)); + QwNeonRegister tmp = i.TempSimd128Register(0); + __ vdup(Neon32, tmp, i.InputRegister(1)); + __ vneg(Neon32, tmp, tmp); + __ vshl(NeonS32, i.OutputSimd128Register(), i.InputSimd128Register(0), + tmp); break; } case kArmI32x4Add: { @@ -1976,8 +1997,11 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( break; } case kArmI32x4ShrU: { - __ vshr(NeonU32, i.OutputSimd128Register(), i.InputSimd128Register(0), - i.InputInt5(1)); + QwNeonRegister tmp = i.TempSimd128Register(0); + __ vdup(Neon32, tmp, i.InputRegister(1)); + __ vneg(Neon32, tmp, tmp); + __ vshl(NeonU32, i.OutputSimd128Register(), i.InputSimd128Register(0), + tmp); break; } case kArmI32x4MinU: { @@ -2029,13 +2053,18 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( break; } case kArmI16x8Shl: { + QwNeonRegister tmp = i.TempSimd128Register(0); + __ vdup(Neon16, tmp, i.InputRegister(1)); __ vshl(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(0), - i.InputInt4(1)); + tmp); break; } case kArmI16x8ShrS: { - __ vshr(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(0), - i.InputInt4(1)); + QwNeonRegister tmp = i.TempSimd128Register(0); + __ vdup(Neon16, tmp, i.InputRegister(1)); + __ vneg(Neon16, tmp, tmp); + __ vshl(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(0), + tmp); break; } case kArmI16x8SConvertI32x4: @@ -2112,8 +2141,11 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( break; } case kArmI16x8ShrU: { - __ vshr(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(0), - i.InputInt4(1)); + QwNeonRegister tmp = i.TempSimd128Register(0); + __ vdup(Neon16, tmp, i.InputRegister(1)); + __ vneg(Neon16, tmp, tmp); + __ vshl(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(0), + tmp); break; } case kArmI16x8UConvertI32x4: @@ -2168,13 +2200,18 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( break; } case kArmI8x16Shl: { + QwNeonRegister tmp = i.TempSimd128Register(0); + __ vdup(Neon8, tmp, i.InputRegister(1)); __ vshl(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(0), - i.InputInt3(1)); + tmp); break; } case kArmI8x16ShrS: { - __ vshr(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(0), - i.InputInt3(1)); + QwNeonRegister tmp = i.TempSimd128Register(0); + __ vdup(Neon8, tmp, i.InputRegister(1)); + __ vneg(Neon8, tmp, tmp); + __ vshl(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(0), + tmp); break; } case kArmI8x16SConvertI16x8: @@ -2237,8 +2274,11 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( break; } case kArmI8x16ShrU: { - __ vshr(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(0), - i.InputInt3(1)); + QwNeonRegister tmp = i.TempSimd128Register(0); + __ vdup(Neon8, tmp, i.InputRegister(1)); + __ vneg(Neon8, tmp, tmp); + __ vshl(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(0), + tmp); break; } case kArmI8x16UConvertI16x8: @@ -3192,6 +3232,8 @@ void CodeGenerator::AssembleReturn(InstructionOperand* pop) { void CodeGenerator::FinishCode() { __ CheckConstPool(true, false); } +void CodeGenerator::PrepareForDeoptimizationExits(int deopt_count) {} + void CodeGenerator::AssembleMove(InstructionOperand* source, InstructionOperand* destination) { ArmOperandConverter g(this, nullptr); diff --git a/deps/v8/src/compiler/backend/arm/instruction-codes-arm.h b/deps/v8/src/compiler/backend/arm/instruction-codes-arm.h index 165ca39f9d..3551e26aea 100644 --- a/deps/v8/src/compiler/backend/arm/instruction-codes-arm.h +++ b/deps/v8/src/compiler/backend/arm/instruction-codes-arm.h @@ -141,6 +141,7 @@ namespace compiler { V(ArmF32x4AddHoriz) \ V(ArmF32x4Sub) \ V(ArmF32x4Mul) \ + V(ArmF32x4Div) \ V(ArmF32x4Min) \ V(ArmF32x4Max) \ V(ArmF32x4Eq) \ diff --git a/deps/v8/src/compiler/backend/arm/instruction-scheduler-arm.cc b/deps/v8/src/compiler/backend/arm/instruction-scheduler-arm.cc index 41d7b4055f..1d7cf61dfe 100644 --- a/deps/v8/src/compiler/backend/arm/instruction-scheduler-arm.cc +++ b/deps/v8/src/compiler/backend/arm/instruction-scheduler-arm.cc @@ -121,6 +121,7 @@ int InstructionScheduler::GetTargetInstructionFlags( case kArmF32x4AddHoriz: case kArmF32x4Sub: case kArmF32x4Mul: + case kArmF32x4Div: case kArmF32x4Min: case kArmF32x4Max: case kArmF32x4Eq: diff --git a/deps/v8/src/compiler/backend/arm/instruction-selector-arm.cc b/deps/v8/src/compiler/backend/arm/instruction-selector-arm.cc index 06aba4491a..ce74faa4a6 100644 --- a/deps/v8/src/compiler/backend/arm/instruction-selector-arm.cc +++ b/deps/v8/src/compiler/backend/arm/instruction-selector-arm.cc @@ -74,17 +74,6 @@ class ArmOperandGenerator : public OperandGenerator { } return false; } - - // Use the stack pointer if the node is LoadStackPointer, otherwise assign a - // register. - InstructionOperand UseRegisterOrStackPointer(Node* node) { - if (node->opcode() == IrOpcode::kLoadStackPointer) { - return LocationOperand(LocationOperand::EXPLICIT, - LocationOperand::REGISTER, - MachineRepresentation::kWord32, sp.code()); - } - return UseRegister(node); - } }; namespace { @@ -102,6 +91,15 @@ void VisitRRR(InstructionSelector* selector, ArchOpcode opcode, Node* node) { g.UseRegister(node->InputAt(1))); } +void VisitSimdShiftRRR(InstructionSelector* selector, ArchOpcode opcode, + Node* node) { + ArmOperandGenerator g(selector); + InstructionOperand temps[] = {g.TempSimd128Register()}; + selector->Emit(opcode, g.DefineAsRegister(node), + g.UseRegister(node->InputAt(0)), + g.UseRegister(node->InputAt(1)), arraysize(temps), temps); +} + void VisitRRRShuffle(InstructionSelector* selector, ArchOpcode opcode, Node* node) { ArmOperandGenerator g(selector); @@ -509,7 +507,8 @@ void InstructionSelector::VisitStore(Node* node) { WriteBarrierKind write_barrier_kind = store_rep.write_barrier_kind(); MachineRepresentation rep = store_rep.representation(); - if (write_barrier_kind != kNoWriteBarrier) { + if (write_barrier_kind != kNoWriteBarrier && + V8_LIKELY(!FLAG_disable_write_barriers)) { DCHECK(CanBeTaggedPointer(rep)); AddressingMode addressing_mode; InstructionOperand inputs[3]; @@ -887,6 +886,15 @@ void InstructionSelector::VisitWord32Xor(Node* node) { VisitBinop(this, node, kArmEor, kArmEor); } +void InstructionSelector::VisitStackPointerGreaterThan( + Node* node, FlagsContinuation* cont) { + Node* const value = node->InputAt(0); + InstructionCode opcode = kArchStackPointerGreaterThan; + + ArmOperandGenerator g(this); + EmitWithContinuation(opcode, g.UseRegister(value), cont); +} + namespace { template <typename TryMatchShift> @@ -1686,17 +1694,17 @@ void VisitWordCompare(InstructionSelector* selector, Node* node, if (TryMatchImmediateOrShift(selector, &opcode, m.right().node(), &input_count, &inputs[1])) { - inputs[0] = g.UseRegisterOrStackPointer(m.left().node()); + inputs[0] = g.UseRegister(m.left().node()); input_count++; } else if (TryMatchImmediateOrShift(selector, &opcode, m.left().node(), &input_count, &inputs[1])) { if (!node->op()->HasProperty(Operator::kCommutative)) cont->Commute(); - inputs[0] = g.UseRegisterOrStackPointer(m.right().node()); + inputs[0] = g.UseRegister(m.right().node()); input_count++; } else { opcode |= AddressingModeField::encode(kMode_Operand2_R); - inputs[input_count++] = g.UseRegisterOrStackPointer(m.left().node()); - inputs[input_count++] = g.UseRegisterOrStackPointer(m.right().node()); + inputs[input_count++] = g.UseRegister(m.left().node()); + inputs[input_count++] = g.UseRegister(m.right().node()); } if (has_result) { @@ -1848,6 +1856,9 @@ void InstructionSelector::VisitWordCompareZero(Node* user, Node* value, return VisitShift(this, value, TryMatchLSR, cont); case IrOpcode::kWord32Ror: return VisitShift(this, value, TryMatchROR, cont); + case IrOpcode::kStackPointerGreaterThan: + cont->OverwriteAndNegateIfEqual(kStackPointerGreaterThanCondition); + return VisitStackPointerGreaterThan(value, cont); default: break; } @@ -2488,7 +2499,7 @@ SIMD_UNOP_LIST(SIMD_VISIT_UNOP) #define SIMD_VISIT_SHIFT_OP(Name) \ void InstructionSelector::Visit##Name(Node* node) { \ - VisitRRI(this, kArm##Name, node); \ + VisitSimdShiftRRR(this, kArm##Name, node); \ } SIMD_SHIFT_OP_LIST(SIMD_VISIT_SHIFT_OP) #undef SIMD_VISIT_SHIFT_OP @@ -2502,6 +2513,14 @@ SIMD_BINOP_LIST(SIMD_VISIT_BINOP) #undef SIMD_VISIT_BINOP #undef SIMD_BINOP_LIST +void InstructionSelector::VisitF32x4Div(Node* node) { + ArmOperandGenerator g(this); + // Use fixed registers in the lower 8 Q-registers so we can directly access + // mapped registers S0-S31. + Emit(kArmF32x4Div, g.DefineAsFixed(node, q0), + g.UseFixed(node->InputAt(0), q0), g.UseFixed(node->InputAt(1), q1)); +} + void InstructionSelector::VisitS128Select(Node* node) { ArmOperandGenerator g(this); Emit(kArmS128Select, g.DefineSameAsFirst(node), |