summaryrefslogtreecommitdiff
path: root/deps/v8/src/arm/assembler-arm.h
diff options
context:
space:
mode:
Diffstat (limited to 'deps/v8/src/arm/assembler-arm.h')
-rw-r--r--deps/v8/src/arm/assembler-arm.h131
1 files changed, 122 insertions, 9 deletions
diff --git a/deps/v8/src/arm/assembler-arm.h b/deps/v8/src/arm/assembler-arm.h
index 1283c3984a..e73c5a170f 100644
--- a/deps/v8/src/arm/assembler-arm.h
+++ b/deps/v8/src/arm/assembler-arm.h
@@ -302,6 +302,20 @@ struct QwNeonRegister {
*m = (encoded_code & 0x10) >> 4;
*vm = encoded_code & 0x0F;
}
+ DwVfpRegister low() const {
+ DwVfpRegister reg;
+ reg.reg_code = reg_code * 2;
+
+ DCHECK(reg.is_valid());
+ return reg;
+ }
+ DwVfpRegister high() const {
+ DwVfpRegister reg;
+ reg.reg_code = reg_code * 2 + 1;
+
+ DCHECK(reg.is_valid());
+ return reg;
+ }
int reg_code;
};
@@ -403,9 +417,11 @@ const QwNeonRegister q15 = { 15 };
// compilation unit that includes this header doesn't use the variables.
#define kFirstCalleeSavedDoubleReg d8
#define kLastCalleeSavedDoubleReg d15
+// kDoubleRegZero and kScratchDoubleReg must pair to form kScratchQuadReg.
#define kDoubleRegZero d14
#define kScratchDoubleReg d15
-
+// After using kScratchQuadReg, kDoubleRegZero must be reset to 0.
+#define kScratchQuadReg q7
// Coprocessor register
struct CRegister {
@@ -624,12 +640,26 @@ class NeonMemOperand BASE_EMBEDDED {
// Class NeonListOperand represents a list of NEON registers
class NeonListOperand BASE_EMBEDDED {
public:
- explicit NeonListOperand(DoubleRegister base, int registers_count = 1);
+ explicit NeonListOperand(DoubleRegister base, int register_count = 1)
+ : base_(base), register_count_(register_count) {}
+ explicit NeonListOperand(QwNeonRegister q_reg)
+ : base_(q_reg.low()), register_count_(2) {}
DoubleRegister base() const { return base_; }
- NeonListType type() const { return type_; }
+ int register_count() { return register_count_; }
+ int length() const { return register_count_ - 1; }
+ NeonListType type() const {
+ switch (register_count_) {
+ default: UNREACHABLE();
+ // Fall through.
+ case 1: return nlt_1;
+ case 2: return nlt_2;
+ case 3: return nlt_3;
+ case 4: return nlt_4;
+ }
+ }
private:
DoubleRegister base_;
- NeonListType type_;
+ int register_count_;
};
@@ -1133,6 +1163,8 @@ class Assembler : public AssemblerBase {
void vmov(const DwVfpRegister dst,
const DwVfpRegister src,
const Condition cond = al);
+ // TODO(bbudge) Replace uses of these with the more general core register to
+ // scalar register vmov's.
void vmov(const DwVfpRegister dst,
const VmovIndex index,
const Register src,
@@ -1313,8 +1345,86 @@ class Assembler : public AssemblerBase {
const NeonMemOperand& dst);
void vmovl(NeonDataType dt, QwNeonRegister dst, DwVfpRegister src);
- // Currently, vswp supports only D0 to D31.
- void vswp(DwVfpRegister srcdst0, DwVfpRegister srcdst1);
+ // Only unconditional core <-> scalar moves are currently supported.
+ void vmov(NeonDataType dt, DwVfpRegister dst, int index, Register src);
+ void vmov(NeonDataType dt, Register dst, DwVfpRegister src, int index);
+
+ void vmov(const QwNeonRegister dst, const QwNeonRegister src);
+ void vmvn(const QwNeonRegister dst, const QwNeonRegister src);
+ void vswp(DwVfpRegister dst, DwVfpRegister src);
+ void vswp(QwNeonRegister dst, QwNeonRegister src);
+ // vdup conditional execution isn't supported.
+ void vdup(NeonSize size, const QwNeonRegister dst, const Register src);
+ void vdup(const QwNeonRegister dst, const SwVfpRegister src);
+
+ void vcvt_f32_s32(const QwNeonRegister dst, const QwNeonRegister src);
+ void vcvt_f32_u32(const QwNeonRegister dst, const QwNeonRegister src);
+ void vcvt_s32_f32(const QwNeonRegister dst, const QwNeonRegister src);
+ void vcvt_u32_f32(const QwNeonRegister dst, const QwNeonRegister src);
+
+ void vabs(const QwNeonRegister dst, const QwNeonRegister src);
+ void vabs(NeonSize size, const QwNeonRegister dst, const QwNeonRegister src);
+ void vneg(const QwNeonRegister dst, const QwNeonRegister src);
+ void vneg(NeonSize size, const QwNeonRegister dst, const QwNeonRegister src);
+ void veor(DwVfpRegister dst, DwVfpRegister src1, DwVfpRegister src2);
+ void vand(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2);
+ void vbsl(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2);
+ void veor(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2);
+ void vorr(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2);
+ void vadd(const QwNeonRegister dst, const QwNeonRegister src1,
+ const QwNeonRegister src2);
+ void vadd(NeonSize size, const QwNeonRegister dst, const QwNeonRegister src1,
+ const QwNeonRegister src2);
+ void vsub(const QwNeonRegister dst, const QwNeonRegister src1,
+ const QwNeonRegister src2);
+ void vsub(NeonSize size, const QwNeonRegister dst, const QwNeonRegister src1,
+ const QwNeonRegister src2);
+ void vmul(const QwNeonRegister dst, const QwNeonRegister src1,
+ const QwNeonRegister src2);
+ void vmul(NeonSize size, const QwNeonRegister dst, const QwNeonRegister src1,
+ const QwNeonRegister src2);
+ void vmin(const QwNeonRegister dst, const QwNeonRegister src1,
+ const QwNeonRegister src2);
+ void vmin(NeonDataType dt, const QwNeonRegister dst,
+ const QwNeonRegister src1, const QwNeonRegister src2);
+ void vmax(const QwNeonRegister dst, const QwNeonRegister src1,
+ const QwNeonRegister src2);
+ void vmax(NeonDataType dt, const QwNeonRegister dst,
+ const QwNeonRegister src1, const QwNeonRegister src2);
+ // vrecpe and vrsqrte only support floating point lanes.
+ void vrecpe(const QwNeonRegister dst, const QwNeonRegister src);
+ void vrsqrte(const QwNeonRegister dst, const QwNeonRegister src);
+ void vrecps(const QwNeonRegister dst, const QwNeonRegister src1,
+ const QwNeonRegister src2);
+ void vrsqrts(const QwNeonRegister dst, const QwNeonRegister src1,
+ const QwNeonRegister src2);
+ void vtst(NeonSize size, const QwNeonRegister dst, const QwNeonRegister src1,
+ const QwNeonRegister src2);
+ void vceq(const QwNeonRegister dst, const QwNeonRegister src1,
+ const QwNeonRegister src2);
+ void vceq(NeonSize size, const QwNeonRegister dst, const QwNeonRegister src1,
+ const QwNeonRegister src2);
+ void vcge(const QwNeonRegister dst, const QwNeonRegister src1,
+ const QwNeonRegister src2);
+ void vcge(NeonDataType dt, const QwNeonRegister dst,
+ const QwNeonRegister src1, const QwNeonRegister src2);
+ void vcgt(const QwNeonRegister dst, const QwNeonRegister src1,
+ const QwNeonRegister src2);
+ void vcgt(NeonDataType dt, const QwNeonRegister dst,
+ const QwNeonRegister src1, const QwNeonRegister src2);
+ void vext(const QwNeonRegister dst, const QwNeonRegister src1,
+ const QwNeonRegister src2, int bytes);
+ void vzip(NeonSize size, const QwNeonRegister dst, const QwNeonRegister src);
+ void vrev16(NeonSize size, const QwNeonRegister dst,
+ const QwNeonRegister src);
+ void vrev32(NeonSize size, const QwNeonRegister dst,
+ const QwNeonRegister src);
+ void vrev64(NeonSize size, const QwNeonRegister dst,
+ const QwNeonRegister src);
+ void vtbl(const DwVfpRegister dst, const NeonListOperand& list,
+ const DwVfpRegister index);
+ void vtbx(const DwVfpRegister dst, const NeonListOperand& list,
+ const DwVfpRegister index);
// Pseudo instructions
@@ -1395,9 +1505,6 @@ class Assembler : public AssemblerBase {
// Debugging
- // Mark generator continuation.
- void RecordGeneratorContinuation();
-
// Mark address of a debug break slot.
void RecordDebugBreakSlot(RelocInfo::Mode mode);
@@ -1611,6 +1718,12 @@ class Assembler : public AssemblerBase {
(reg.reg_code < LowDwVfpRegister::kMaxNumLowRegisters);
}
+ bool VfpRegisterIsAvailable(QwNeonRegister reg) {
+ DCHECK(reg.is_valid());
+ return IsEnabled(VFP32DREGS) ||
+ (reg.reg_code < LowDwVfpRegister::kMaxNumLowRegisters / 2);
+ }
+
private:
int next_buffer_check_; // pc offset of next buffer check
generated by cgit v1.2.3 (git 2.39.1) at 2024-06-02 22:44:30 +0000