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| author | Shigeki Ohtsu <ohtsu@ohtsu.org> | 2017-11-03 00:22:35 +0900 |
|---|---|---|
| committer | Myles Borins <mylesborins@google.com> | 2017-11-03 12:22:29 -0500 |
| commit | e7fff9c4435f9f5ef8069217d2a0093c81a8c78b (patch) | |
| tree | 45fbbf4aae64902b831501231d16b7a0af2aeb53 /deps/openssl/openssl/crypto/x86_64cpuid.pl | |
| parent | 3d4d5e0c60f00693947c940b09249f3952bb0cdc (diff) | |
| download | android-node-v8-e7fff9c4435f9f5ef8069217d2a0093c81a8c78b.tar.gz android-node-v8-e7fff9c4435f9f5ef8069217d2a0093c81a8c78b.tar.bz2 android-node-v8-e7fff9c4435f9f5ef8069217d2a0093c81a8c78b.zip | |
deps: upgrade openssl sources to 1.0.2m
This replaces all sources of openssl-1.0.2m.tar.gz into
deps/openssl/openssl
PR-URL: https://github.com/nodejs/node/pull/16691
Reviewed-By: Ben Noordhuis <info@bnoordhuis.nl>
Reviewed-By: Tobias Nießen <tniessen@tnie.de>
Reviewed-By: Michael Dawson <michael_dawson@ca.ibm.com>
Reviewed-By: Myles Borins <myles.borins@gmail.com>
Reviewed-By: Colin Ihrig <cjihrig@gmail.com>
Reviewed-By: Rod Vagg <rod@vagg.org>
Reviewed-By: Gireesh Punathil <gpunathi@in.ibm.com>
Reviewed-By: James M Snell <jasnell@gmail.com>
Diffstat (limited to 'deps/openssl/openssl/crypto/x86_64cpuid.pl')
| -rw-r--r-- | deps/openssl/openssl/crypto/x86_64cpuid.pl | 19 |
1 files changed, 17 insertions, 2 deletions
diff --git a/deps/openssl/openssl/crypto/x86_64cpuid.pl b/deps/openssl/openssl/crypto/x86_64cpuid.pl index a3d6f438f9..ef3608b134 100644 --- a/deps/openssl/openssl/crypto/x86_64cpuid.pl +++ b/deps/openssl/openssl/crypto/x86_64cpuid.pl @@ -136,8 +136,19 @@ OPENSSL_ia32_cpuid: or \$0x40000000,%edx # set reserved bit#30 on Intel CPUs and \$15,%ah cmp \$15,%ah # examine Family ID - jne .Lnotintel + jne .LnotP4 or \$0x00100000,%edx # set reserved bit#20 to engage RC4_CHAR +.LnotP4: + cmp \$6,%ah + jne .Lnotintel + and \$0x0fff0ff0,%eax + cmp \$0x00050670,%eax # Knights Landing + je .Lknights + cmp \$0x00080650,%eax # Knights Mill (according to sde) + jne .Lnotintel +.Lknights: + and \$0xfbffffff,%ecx # clear XSAVE flag to mimic Silvermont + .Lnotintel: bt \$28,%edx # test hyper-threading bit jnc .Lgeneric @@ -162,6 +173,10 @@ OPENSSL_ia32_cpuid: mov \$7,%eax xor %ecx,%ecx cpuid + bt \$26,%r9d # check XSAVE bit, cleared on Knights + jc .Lnotknights + and \$0xfff7ffff,%ebx # clear ADCX/ADOX flag +.Lnotknights: mov %ebx,8(%rdi) # save extended feature flags .Lno_extended_info: @@ -175,7 +190,7 @@ OPENSSL_ia32_cpuid: .Lclear_avx: mov \$0xefffe7ff,%eax # ~(1<<28|1<<12|1<<11) and %eax,%r9d # clear AVX, FMA and AMD XOP bits - andl \$0xffffffdf,8(%rdi) # cleax AVX2, ~(1<<5) + andl \$0xffffffdf,8(%rdi) # clear AVX2, ~(1<<5) .Ldone: shl \$32,%r9 mov %r10d,%eax |