diff options
| author | Daniel Bevenius <daniel.bevenius@gmail.com> | 2017-05-26 07:27:45 +0200 |
|---|---|---|
| committer | Shigeki Ohtsu <ohtsu@ohtsu.org> | 2017-06-03 00:41:47 +0900 |
| commit | bd4a53493b4d130e39955a2497995707666cffd4 (patch) | |
| tree | ca6d428d3eca9528608af14f0d969f8999e87c64 /deps/openssl/openssl/crypto/x86_64cpuid.pl | |
| parent | a235e670a820107210be27e0cd266164763fb014 (diff) | |
| download | android-node-v8-bd4a53493b4d130e39955a2497995707666cffd4.tar.gz android-node-v8-bd4a53493b4d130e39955a2497995707666cffd4.tar.bz2 android-node-v8-bd4a53493b4d130e39955a2497995707666cffd4.zip | |
deps: upgrade openssl sources to 1.0.2l
This replaces all sources of openssl-1.0.2l.tar.gz into
deps/openssl/openssl
Fixes: https://github.com/nodejs/node/issues/13161
PR-URL: https://github.com/nodejs/node/pull/13233
Reviewed-By: Shigeki Ohtsu <ohtsu@ohtsu.org>
Reviewed-By: Sam Roberts <vieuxtech@gmail.com>
Reviewed-By: Michael Dawson <michael_dawson@ca.ibm.com>
Diffstat (limited to 'deps/openssl/openssl/crypto/x86_64cpuid.pl')
| -rw-r--r-- | deps/openssl/openssl/crypto/x86_64cpuid.pl | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/deps/openssl/openssl/crypto/x86_64cpuid.pl b/deps/openssl/openssl/crypto/x86_64cpuid.pl index d208d02392..a3d6f438f9 100644 --- a/deps/openssl/openssl/crypto/x86_64cpuid.pl +++ b/deps/openssl/openssl/crypto/x86_64cpuid.pl @@ -59,7 +59,7 @@ OPENSSL_ia32_cpuid: mov %rbx,%r8 # save %rbx xor %eax,%eax - mov %eax,8(%rdi) # clear 3rd word + mov %eax,8(%rdi) # clear extended feature flags cpuid mov %eax,%r11d # max value for standard query level @@ -127,14 +127,6 @@ OPENSSL_ia32_cpuid: shr \$14,%r10d and \$0xfff,%r10d # number of cores -1 per L1D - cmp \$7,%r11d - jb .Lnocacheinfo - - mov \$7,%eax - xor %ecx,%ecx - cpuid - mov %ebx,8(%rdi) - .Lnocacheinfo: mov \$1,%eax cpuid @@ -164,6 +156,15 @@ OPENSSL_ia32_cpuid: or %ecx,%r9d # merge AMD XOP flag mov %edx,%r10d # %r9d:%r10d is copy of %ecx:%edx + + cmp \$7,%r11d + jb .Lno_extended_info + mov \$7,%eax + xor %ecx,%ecx + cpuid + mov %ebx,8(%rdi) # save extended feature flags +.Lno_extended_info: + bt \$27,%r9d # check OSXSAVE bit jnc .Lclear_avx xor %ecx,%ecx # XCR0 |