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| author | Sam Roberts <vieuxtech@gmail.com> | 2018-11-22 10:39:20 -0800 |
|---|---|---|
| committer | Sam Roberts <vieuxtech@gmail.com> | 2019-01-22 13:32:34 -0800 |
| commit | 4231ad04f0b2aee5bda6be94715d4b70badaac8b (patch) | |
| tree | 19f189fae6828708ebd37e466ce4a7716494b96a /deps/openssl/openssl/crypto/camellia/asm/cmllt4-sparcv9.pl | |
| parent | 5d80f9ea6091847176fa47fb1395fdffc4af9164 (diff) | |
| download | android-node-v8-4231ad04f0b2aee5bda6be94715d4b70badaac8b.tar.gz android-node-v8-4231ad04f0b2aee5bda6be94715d4b70badaac8b.tar.bz2 android-node-v8-4231ad04f0b2aee5bda6be94715d4b70badaac8b.zip | |
deps: upgrade openssl sources to 1.1.1a
This updates all sources in deps/openssl/openssl with openssl-1.1.1a.
PR-URL: https://github.com/nodejs/node/pull/25381
Reviewed-By: Daniel Bevenius <daniel.bevenius@gmail.com>
Reviewed-By: Shigeki Ohtsu <ohtsu@ohtsu.org>
Diffstat (limited to 'deps/openssl/openssl/crypto/camellia/asm/cmllt4-sparcv9.pl')
| -rw-r--r-- | deps/openssl/openssl/crypto/camellia/asm/cmllt4-sparcv9.pl | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/deps/openssl/openssl/crypto/camellia/asm/cmllt4-sparcv9.pl b/deps/openssl/openssl/crypto/camellia/asm/cmllt4-sparcv9.pl index ffe4a7d91c..6396679a5a 100644 --- a/deps/openssl/openssl/crypto/camellia/asm/cmllt4-sparcv9.pl +++ b/deps/openssl/openssl/crypto/camellia/asm/cmllt4-sparcv9.pl @@ -8,8 +8,8 @@ # ==================================================================== -# Written by David S. Miller <davem@devemloft.net> and Andy Polyakov -# <appro@openssl.org>. The module is licensed under 2-clause BSD +# Written by David S. Miller and Andy Polyakov. +# The module is licensed under 2-clause BSD # license. October 2012. All rights reserved. # ==================================================================== @@ -17,7 +17,7 @@ # Camellia for SPARC T4. # # As with AES below results [for aligned data] are virtually identical -# to critical path lenths for 3-cycle instruction latency: +# to critical path lengths for 3-cycle instruction latency: # # 128-bit key 192/256- # CBC encrypt 4.14/4.21(*) 5.46/5.52 @@ -25,7 +25,7 @@ # misaligned data. # # As with Intel AES-NI, question is if it's possible to improve -# performance of parallelizeable modes by interleaving round +# performance of parallelizable modes by interleaving round # instructions. In Camellia every instruction is dependent on # previous, which means that there is place for 2 additional ones # in between two dependent. Can we expect 3x performance improvement? |